MX2016003228A - Dispositivo de procesamiento de datos y metodo de procesamiento de datos. - Google Patents

Dispositivo de procesamiento de datos y metodo de procesamiento de datos.

Info

Publication number
MX2016003228A
MX2016003228A MX2016003228A MX2016003228A MX2016003228A MX 2016003228 A MX2016003228 A MX 2016003228A MX 2016003228 A MX2016003228 A MX 2016003228A MX 2016003228 A MX2016003228 A MX 2016003228A MX 2016003228 A MX2016003228 A MX 2016003228A
Authority
MX
Mexico
Prior art keywords
parity
data processing
ldpc
bits
matrix
Prior art date
Application number
MX2016003228A
Other languages
English (en)
Inventor
Yuji Shinohara
Makiko Yamamoto
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of MX2016003228A publication Critical patent/MX2016003228A/es

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
    • H03M13/356—Unequal error protection [UEP]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard
    • H03M13/6552—DVB-T2
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard
    • H03M13/6555—DVB-C2
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • General Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Computational Mathematics (AREA)
  • Multimedia (AREA)
  • Algebra (AREA)
  • Computing Systems (AREA)
  • Error Detection And Correction (AREA)

Abstract

La tecnología presente se relaciona a un dispositivo de procesamiento de datos y a un método de procesamiento de datos de modo que se proporciona el código LDPC con una velocidad de error de bit buena. Un codificador LDPC codifica mediante un código LDPC cuya longitud de código es de 64800 bits y una velocidad es de 7/15. El código LDCP incluye los bits de información y los bits de paridad. Una matriz H de verificación de paridad incluye una parte de la matriz de información que corresponde a los bits de información del código LDPC y una parte de la matriz de paridad que corresponde a los bits de paridad. La parte de la matriz de información de la matriz H de verificación de paridad está representada por una tabla de valor inicial de la matriz de verificación de paridad que indica una posición de un elemento 1 de la parte de la matriz de información para cada una de las 360 columnas. La tecnología presente es aplicable a un caso en el cual se realizan la codificación LDPC y la decodificación LDPC.
MX2016003228A 2013-09-20 2014-09-05 Dispositivo de procesamiento de datos y metodo de procesamiento de datos. MX2016003228A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013196140 2013-09-20
PCT/JP2014/073467 WO2015041072A1 (ja) 2013-09-20 2014-09-05 データ処理装置、及びデータ処理方法

Publications (1)

Publication Number Publication Date
MX2016003228A true MX2016003228A (es) 2016-06-07

Family

ID=52688723

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2016003228A MX2016003228A (es) 2013-09-20 2014-09-05 Dispositivo de procesamiento de datos y metodo de procesamiento de datos.

Country Status (8)

Country Link
US (1) US20160211866A1 (es)
EP (1) EP3048736A4 (es)
JP (1) JPWO2015041072A1 (es)
KR (1) KR20160060026A (es)
CN (1) CN105556853A (es)
CA (1) CA2923593A1 (es)
MX (1) MX2016003228A (es)
WO (1) WO2015041072A1 (es)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160336968A1 (en) * 2015-05-11 2016-11-17 Comtech Ef Data Corp. System and method for encoding and decoding using a plurality of constellations within a single fec block
CN109792309B (zh) * 2016-08-10 2021-12-31 瑞典爱立信有限公司 传输块内的校验位置

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2454193B (en) * 2007-10-30 2012-07-18 Sony Corp Data processing apparatus and method
JP4224777B2 (ja) 2003-05-13 2009-02-18 ソニー株式会社 復号方法および復号装置、並びにプログラム
JP4688841B2 (ja) * 2007-03-20 2011-05-25 日本放送協会 符号化器及び復号器、並びに送信装置及び受信装置
DK2056464T3 (da) * 2007-10-30 2013-02-18 Sony Corp Databehandlingsanordning og -fremgangsmåde
TWI459724B (zh) * 2007-11-26 2014-11-01 Sony Corp Data processing device and data processing method
PT2509270T (pt) * 2007-11-26 2017-07-18 Sony Corp Aparelho de processamento de dados e método de processamento de dados bem como aparelho de descodificação e método de descodificação
TWI390856B (zh) * 2007-11-26 2013-03-21 Sony Corp Data processing device and data processing method
TWI410055B (zh) * 2007-11-26 2013-09-21 Sony Corp Data processing device, data processing method and program product for performing data processing method on computer
TWI497920B (zh) * 2007-11-26 2015-08-21 Sony Corp Data processing device and data processing method
PL2091156T3 (pl) * 2008-02-18 2014-01-31 Samsung Electronics Co Ltd Urządzenie i sposób do kodowania i dekodowania kanału w systemie komunikacyjnym z wykorzystaniem kodów kontroli bitów parzystości o niskiej gęstości
JP5500379B2 (ja) * 2010-09-03 2014-05-21 ソニー株式会社 データ処理装置、及びデータ処理方法
JP5505725B2 (ja) * 2010-09-16 2014-05-28 ソニー株式会社 データ処理装置、及びデータ処理方法
KR101702358B1 (ko) * 2011-01-06 2017-02-03 삼성전자주식회사 저밀도 패리티 검사 코드를 사용하는 통신 시스템에서의 채널 부호화/복호화 방법 및 장치
JP5664919B2 (ja) * 2011-06-15 2015-02-04 ソニー株式会社 データ処理装置、及び、データ処理方法
EP2560311A1 (en) * 2011-08-17 2013-02-20 Panasonic Corporation Cyclic-block permutations for spatial multiplexing with quasi-cyclic LDPC codes
US20150046766A1 (en) * 2013-02-08 2015-02-12 Sony Corporation Data processing apparatus and data processing method
MX2014011863A (es) * 2013-02-08 2014-11-03 Sony Corp Dispositivo de procesamiento de datos y metodo de procesamiento de datos.
CN104969478B (zh) * 2013-02-08 2019-05-07 索尼公司 数据处理装置以及数据处理方法
WO2014123014A1 (ja) * 2013-02-08 2014-08-14 ソニー株式会社 データ処理装置、及びデータ処理方法
KR20150005853A (ko) * 2013-07-05 2015-01-15 삼성전자주식회사 송신 장치 및 그의 신호 처리 방법
KR20160061328A (ko) * 2013-09-26 2016-05-31 소니 주식회사 데이터 처리 장치 및 데이터 처리 방법
US20160211868A1 (en) * 2013-09-26 2016-07-21 Sony Corporation Data processing device and data processing method

Also Published As

Publication number Publication date
EP3048736A4 (en) 2017-05-24
JPWO2015041072A1 (ja) 2017-03-02
KR20160060026A (ko) 2016-05-27
WO2015041072A1 (ja) 2015-03-26
CN105556853A (zh) 2016-05-04
CA2923593A1 (en) 2015-03-26
EP3048736A1 (en) 2016-07-27
US20160211866A1 (en) 2016-07-21

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