KR980004783A - Digital Signal Processing Equipment - Google Patents
Digital Signal Processing Equipment Download PDFInfo
- Publication number
- KR980004783A KR980004783A KR1019960019658A KR19960019658A KR980004783A KR 980004783 A KR980004783 A KR 980004783A KR 1019960019658 A KR1019960019658 A KR 1019960019658A KR 19960019658 A KR19960019658 A KR 19960019658A KR 980004783 A KR980004783 A KR 980004783A
- Authority
- KR
- South Korea
- Prior art keywords
- data
- signal processing
- digital signal
- ecc
- sync
- Prior art date
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information
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- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
본 발명은 가변 데이타의 처리가 가능한 하나의 ECC를 이용하여 싱크 블럭 데이타와 서브 코드 데이타의 에러 정정이 가능토록 하는 디지탈 신호처리장치를 제공한다.The present invention provides a digital signal processing apparatus that enables error correction of sync block data and sub code data using one ECC capable of processing variable data.
본 발명은 기록시에는 식별코드 처리부에 위치하고 재생시에는 ECC수단에 위치하여 입력되는 디지탈 데이타로부터 서브 코드 싱크와 블럭 싱크를 검출하여 제어신호를 출력하는 동기 검출부와, 상기 동기 검출부의 출력에 따라 싱크 블럭 데이타와 서브 코드 데이타를 겸용으로 에러 정정하는 ECC부를 구비한다.According to the present invention, a sync detection unit detects a sub code sync and a block sync from an input digital data and is located in an ECC means at the time of recording, and outputs a control signal. An ECC unit for error correction of both data and sub code data is provided.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2도는 본 발명에 따른 디지탈 신호처리장치의 구성 블록도.2 is a block diagram of a digital signal processing apparatus according to the present invention.
제3도는 제2도의 데이타 크기 검출부의 상세 구성도.3 is a detailed block diagram of the data size detection unit of FIG.
제4도(가)-(다)는 제2도 및 제3도의 각 신호 타이밍도.4 (a)-(c) are signal timing diagrams of FIGS. 2 and 3;
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960019658A KR100192409B1 (en) | 1996-06-03 | 1996-06-03 | Digital signal processing apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960019658A KR100192409B1 (en) | 1996-06-03 | 1996-06-03 | Digital signal processing apparatus |
Publications (2)
Publication Number | Publication Date |
---|---|
KR980004783A true KR980004783A (en) | 1998-03-30 |
KR100192409B1 KR100192409B1 (en) | 1999-06-15 |
Family
ID=19460693
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960019658A KR100192409B1 (en) | 1996-06-03 | 1996-06-03 | Digital signal processing apparatus |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100192409B1 (en) |
-
1996
- 1996-06-03 KR KR1019960019658A patent/KR100192409B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100192409B1 (en) | 1999-06-15 |
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