KR970076254A - 신호 프로세싱 응용에 사용하는 재구성가능한 컴퓨터 구조 - Google Patents

신호 프로세싱 응용에 사용하는 재구성가능한 컴퓨터 구조 Download PDF

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KR970076254A
KR970076254A KR1019970021457A KR19970021457A KR970076254A KR 970076254 A KR970076254 A KR 970076254A KR 1019970021457 A KR1019970021457 A KR 1019970021457A KR 19970021457 A KR19970021457 A KR 19970021457A KR 970076254 A KR970076254 A KR 970076254A
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configurable logic
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찰리 알. 루프
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클라크 3세 존 엠
내셔널 세미컨덕터 코오포레이션
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

센서 데이터 프로세싱을 포함한 특정 계산 응용을 위한 저 비용의 고 성능 시스템에 대한 정보 프로세싱 장치용 구조. 본 발명의 재구성가능한 프로세서 구성은 ALP(Adaptive Logic Processor)라 불리는 프로그램가능한 논리구조를 사용한다. 이 구조는 확장가능한 FPGA(Field Programmable Gate Array)와 유사하고 프로그램 특정 파이프라인 기능의 실행을 위해 최적화되며, 이 기능은 계산의 진행동안 수회 변화될 수 있다. RPIC(Reconfiguration Pipeline Intruction Control) 유닛은 구성 프로세서에서 파이프라인 기능을 ALP로 로드하고 메모리와, I/O 장치 및, 연산 프로세싱 유닛 등의 다른 정보 프로세싱 구조로 ALP의 동작을 조정하기 위해 사용된다. 본 발명의 재구성가능한 구성을 가진 다중 소자는 결합되어y번째 SIMD(Singoe instruction Multiple Data) 구성 개념을 기준으로 고성능 병렬 프로세싱 시스템을 구성한다.

Description

신호 프로세싱 응용에 사용하는 재구성가능한 컴퓨터 구조
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 재구성가능한 신호 프로세싱 시스템의 기초가 되는 계산 방법을 도시한 다이어그램.
제30도는 본 발명의 구조를 기준으로 한 이미지 프로세싱 응용을 위한 16 RSP 데이터 프로세서에 대한 매크로 블록에서 화소의 매핑도.
제32도는 본 발명의 구조를 기준으로 한 이동 오프셋 검출 응용에 대한 일반적인 검색 계획도.

Claims (6)

  1. 적응적 논리 프로세서의 소자를 포함하는 재구성가능한 계산 장치에 있어서, 상기 적응적 논리 프로세서는 구성가능한 논리 셀의 복수의 수직 열과 구성가능한 논리 셀의 복수의 수평 행을 포함하는 어레이내에 정렬된 개별적으로 구성가능한 복수의 논리 셀과, 제어 신호의 전송을 위한 제어선 세트와 파이프라인 세그먼트와 논리셀 재구성 제어기 사이의 데이터 전송을 위한 데이터선 세트로서, 상기 파이프라인 세그먼트는 구성된 논리 셀 세트를 포함하고 어레이의 수직 영역을 따라 위치되며, 상기 제어선 세트와 데이터선 세트는 어레이의 복수의 열을 가로질러 연장되어 있어, 상기 파이프라인 세그먼트가 어레이의 복수의 수평 위치에 위치되도록 하는 제어선 세트 및 데이터선 세트와, 상기 파이프라인 세그먼트를 형성하는 논리 셀의 구성과, 구성된 논리 셀에 의한 논리 기능 세트의 실행을 제어 신호선과 데이터선에 의해 명령 및 데이터를 전송함으로써 제어하는 논리 셀 재구성 제어기를 포함하는 것을 특징으로 하는 재구성가능한 계산 장치.
  2. 제1항에 있어서, 스칼라 연산 기능을 실행하기 위한 연산 프로세싱 유닛을 추가로 포함하며, 상기 적응적 논리 프로세서는 파이프라인 세그먼트내에 포함된 구성된 논리 셀 세트와 연산 프로세싱 유닛 사이의 데이터 전송을 위한 제2데이터선 세트를 추가로 포함하며, 상기 제2데이터선 세트는 어레이의 각각의 열을 가로질러 연장되어 있는 것을 특징으로 하는 재구성가능한 계산 장치.
  3. 제1항에 있어서, 상기 적응적 논리 프로세서는, 구성가능한 논리 셀의 인접한 행들 사이에 이어져서 이 인접한 행내의 구성가능한 논리 셀들이 있는 선택적으로 접속될 수 있는 행 로컬 버스와, 선택된 구성가능한 논리 셀이 선택된 행 로컬 버스로부터 데이터를 판독하거나 상기 로컬 버스에 데이터를 기록하도록 하기 위해, 선택된 구성가능한 논리 셀과 선택된 행 로컬 버스 사이에 선택적으로 접속가능한 논리 셀-대-로컬 버스 인터페이스 회로군과, 선택된 구성가능한 논리 셀에 의해 제공된 출력 신호가 행 로컬 버스와 상관없이 인접한 구성가능한 논리 셀에 입력 신호로서 직접 제공될 수 있도록, 상기 선택된 구성가능한 논리 셀과 인접한 구성가능한 논리 셀 사이에 접속가능한 직접 상호접속 수단을 추가로 포함하는 것을 특징으로 하는 재구성가능한 계산 장치.
  4. 재구성가능한 계산 시스템에 있어서, 상호접속되며 재구성가능한 복수의 계산 장치를 포함하고, 각각의 재구성가능한 계산 장치는 적응적 논리 프로세서와, 복수의 재구성가능한 계산 장치들 사이에서 신호 전송을 제공하기 위한 상호접속 버스로서, 상호접속의 네트 신호 대역폭은 상호접속된 재구성가능한 계산 장치의 수와 비례하여 증가하는 상호접속 버스의 소자들을 추가로 포함하며, 상기 적응적 논리 프로세서는, 구성가능한 논리 셀의 복수의 수직열과 구성가능한 논리 셀의 복수의 수평행을 포함하는 어레이내에 정렬된 개별적으로 구성가능한 복수의 논리 셀과, 제어신호 전송용 제어선 세트와 파이프라인 세그먼트와 논리 셀 재구성 제어기 사이의 데이터 전송용 데이터선 세트로서, 상기 파이프라인 세그먼트는 구성된 논리 셀 세트를 포함하고 어레이의 수직 영역을 따라 위치되어 있으며, 상기 제어선 세트와 데이터선 세트는 어레이의 복수의 열을 가로질러 연장되어, 파이프라인 세그먼트를 어레이의 복수의 수평 위치에 위치되도록 하는 제어선 세트 및 데이터선 세트와, 상기 파이프라인 세그먼트를 형성하는 논리 셀의 구성과, 구성된 논리셀에 의한 논리 함수 세트의 실행을 상기 제어 신호선과 데이터선에 의해 명령 및 데이터를 전송함으로써 제어하기 위한 논리 셀 재구성 제어기를 추가로 포함하는 것을 특징으로 하는 재구성 가능한 계산 시스템.
  5. 제4항에 있어서, 상기 각각의 재구성가능한 계산 장치는, 스칼라 연산 기능을 실행하는 연산 프로세싱 유닛을 추가로 포함하며, 각각의 장치내의 상기 적응적 논리 프로세서는, 각각의 적응적 논리 프로세서의 파이프라인 세그먼트내에 포함된 구성된 논리 셀 세트와 연산 프로세싱 유닛 사이의 데이터 전송을 위해 어레이의 각각의 열을 가로질러 연장되어 있는 제2데이터선 세트를 추가로 포함하는 것을 특징으로 하는 재구성가능한 계산시스템.
  6. 제4항에 있어서, 상기 각각의 재구성가능한 계산 장치의 적응적 논리 프로세서는, 선택적으로 접속가능한 상기 인접 행들내의 구성가능한 논리 셀의 인접행들 사이에 이어져 있는 행 로컬 버스와, 선택된 구성가능한 논리 셀과 선택된 행 로컬 버스 사이에 선택적으로 접속가능하여 상기 선택된 구성가능한 논리 셀이 상기 선택된 행 로컬 버스로부터 데이터를 판독하거나 상기 로컬 버스에 데이터를 기록하도록 하는 논리 셀-대-로컬 버스 인터페이스 회로군 및 상기 선택된 구성가능한 논리 셀에 의해 제공된 출력 신호가 상기 행 로컬 버스와 관례없이 인접한 구성가능한 논리 셀에 입력 신호로서 직접 제공될 수 있도록, 상기 선택된 구성가능한 논리 셀과 인접한 구성가능한 논리 셀 사이에 접속가능한 직접 상호접속 수단을 추가로 포함하는 것을 특징으로 한 재구성가능한 계산 시스템.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019970021457A 1996-05-28 1997-05-28 신호프로세싱응용에사용하는재구성가능한컴퓨터구조 KR100305947B1 (ko)

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US08/654,395 1996-05-28
US08/654,395 US5784636A (en) 1996-05-28 1996-05-28 Reconfigurable computer architecture for use in signal processing applications

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KR100893527B1 (ko) * 2007-02-02 2009-04-17 삼성전자주식회사 재구성 가능 멀티 프로세서 시스템에서의 매핑 및 스케줄링방법

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