KR970069482A - 반도체 장치 및 그의 제조방법과 그의 실장방법 - Google Patents

반도체 장치 및 그의 제조방법과 그의 실장방법 Download PDF

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KR970069482A
KR970069482A KR1019970013812A KR19970013812A KR970069482A KR 970069482 A KR970069482 A KR 970069482A KR 1019970013812 A KR1019970013812 A KR 1019970013812A KR 19970013812 A KR19970013812 A KR 19970013812A KR 970069482 A KR970069482 A KR 970069482A
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electrodes
solder bump
substrate
semiconductor device
bump electrodes
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KR1019970013812A
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히데코 안도오
히로시 기쿠치
토시히코 사토오
테쯔야 하야시다
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가나이 쓰토무
가부시키가이샤 히타치세이사쿠쇼
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Publication of KR970069482A publication Critical patent/KR970069482A/ko

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    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B60J5/10—Doors arranged at the vehicle rear
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

방열성 및 전기적 신뢰성이 개선된 반도체장치 및 그의 실행방법이 개시되어 있다. 구체적으로 설명하면 본 발명의 반도체장치는, 배선기판과, 상기 배선기판의 일주면에 탑재된 반도체칩과, 반도체 칩상에 탑재된 방열핀과, 상기 배선기판의 이면에 형성된 복수의 제1땜납 범프 전극 및 복수의 제2땜납 범프 전극을 가지며, 상기 기판의 두깨방향의 상기 제2땜납 범프 전극의 높이는, 상기 기판의 두께 방향의 상기 제1땜납 범프 전극의 높이 보다 낮으며, 상기 제2땜납 범프 전극의 용융점은, 상기 제1땜납 범프 전극의 용융점보다 높다. 또한, 상기 반도체 장치는 상기 복수의 제1땜납 범프 전극이 실장기판의 대응하는 전극상에 배치되도록 상기 실장기판상에 탑재되며, 그후 상기 제1땜납 범프 전극의 용융점보다 높으며, 또한, 상기 제2땜납 범프전극의 용융점 보다도 낮은 온도의 열처리로 상기 복수의 제1땜납 범프 전극을 용융시킴으로써 상기 제1땜납 범프전극과 상기 실장기판의 대응하는 전극을 기계적, 전기적으로 접속한다. 상기 제2땜납 범프 전극을 기계적, 전기적으로 접속한다. 상기 제2땜납 범프 전극은, 상기 반도체 장치의 기판과 상기 실장기판 사이의 거리를 실질적으로 규정한다.

Description

반도체 장치 및 그의 제조방법과 그의 실장방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시형태인 반도체 장치의 단면도, 제2도는 상기 반도체 장치의 주요부 확대 단면도.

Claims (8)

  1. (1) 제1주면 및 상기 제1주면에 대향하는 제2주면을 가지고, 복수의 배선과 상기 제1주면상에 형성된 복수의 제1전극과 상기 제2주면상에 형성된 복수의 제2전극 및 복수의 제3전극을 가지는 기판과; (2) 그의 주면에 상기 복수의 제1전극과 전기적으로 접속되는 복수의 본딩패드를 가지는, 상기 제1주면상에 탑재된 반도체 칩과; (3) 상기 복수의 제2전극의 표면에 형성된 복수의 제1땜납 범프 전극과 상기 복수의 제3전극 표면에 형성된 복수의 제2땜납 범프 전극; 을 포함하며, 상기 복수의 제1전극과 상기 복수의 제2전극은 상기 복수의 배선에 의해 전기적으로 접속되어 있으며, 상기 기판의 두께방향의 상기 제2땜납 범프전극의 높이는, 상기 기판의 두께 방향의 상기 제1땜납 범프 전극의 높이 보다 낮으며, 상기 제2땜납 범프전극의 용융점은, 상기 제1땜납 범프 전극의 용융점보다 높은 것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 상기 복수의 제3전극 및 상기 복수의 제2땜납 범프전극의 각각은, 상기 반도체 칩과 전기적으로 접속되어 있지 않을 것을 특징으로 하는 반도체장치.
  3. 제1항에 있어서, 상기 기판은 거의 사각형이며, 상기 복수의 제3전극 및 상기 복수의 제2땜납 범프 전극의 각각은, 상기 기판의 주변부에 배치되어 있는 것을 특징으로 하는 반도체장치.
  4. 제1항에 있어서, 상기 반도체 칩상에 고정되어 있는 히트 스프레더(heat spreader)를 더 포함한 것을 특징으로 하는 반도체 장치.
  5. (1) 제1주면 및 상기 제1주면에 대향하는 제2주면을 가지고, 복수의 배선과 상기 제1주면상에 형성된 복수의 제1전극과 상기 제2주면상에 형성된 복수의 제2전극 및 복수의 제3전극을 가지는 기판을 준비하는 단계와; (2) 그의 주면에 복수의 본딩패드가 형성된 반도체 칩을 상기 기판의 제1주면상에 탑재하여 상기 복수의 제1전극과 상기 복수의 본딩패드가 전기적으로 접속되도록 한는 단계와; (3) 상기 복수의 제2전극의 표면에 복수의 제1땜납 범프전극을 형성하고, 상기 복수의 제3전극의 표면에 복수의 제2땜납 범프 전극을 형성하여, 상기 기판, 상기 반도체칩, 상기 복수의 제1 및 제2땜납 범프전극을 포함하는 반도체 장치를 생성시키는 단계와; (4) 상기 반도체 장치를 실장기판상에 탑재하여 상기 복수의 제1땜납 범프전극이 상기 실장기판의 대응하는 전극상에 배치되도록 하는 단계와; (5) 상기 제1땜납 범프전극의 용융점 보다 높으며 또한 상기 제2땜납 범프전극의 용융점보다 낮은 온도의 열처리로, 상기 복수의 제1땜납 범프 전극을 용융시켜, 상기 제1땜납 범프 전극과 상기 실장기판의 대응하는 전극을 기계적, 전기적으로 접속하는 단계; 를 포함하고, 상기 복수의 제1전극과 상기 복수의 제2전극은 상기 복수의 배선에 의해 전기적으로 접속되어 있으며, 상기 기판의 두께 방향의 상기 제2땜납 범프전극의 높이는 상기 기판의 두께방향의 상기 제1땜납 범프 전극의 높이보다 낮으며, 상기 제2땜납 범프전극의 용융점은 상기 제1땜납 범프전극의 용융점보다 높은 것을 특징으로 하는 반도체 장치 실장방법.
  6. 제5항에 있어서, 상기 복수의 제2땜납 범프전극의 각각은 상기 기판과 상기 실장 기판 사이의 거리를 실질적으로 규정하는 것을 특징으로 하는 반도체 장치 실장방법.
  7. 제6항에 있어서, 상기 기판은 거의 사각형이며, 상기 복수의 제3전극 및 상기 제2땜납 범프전극의 각각은, 상기 기판의 주변부에 배치되어 있는 것을 특징으로 하는 반도체 장치 실장방법.
  8. 제5항에 있어서, 상기 단계(4)와 (5)이전에 히트 스프레더를상기 반도체 칩사에 고정하는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치 실장방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019970013812A 1996-04-25 1997-04-15 반도체 장치 및 그의 제조방법과 그의 실장방법 KR970069482A (ko)

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JP10496396A JP3688801B2 (ja) 1996-04-25 1996-04-25 半導体装置及びその製造方法並びにその実装方法
JP96-104963 1996-04-25

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Publication number Priority date Publication date Assignee Title
JP3328157B2 (ja) * 1997-03-06 2002-09-24 シャープ株式会社 液晶表示装置
JP2003100801A (ja) * 2001-09-25 2003-04-04 Mitsubishi Electric Corp 半導体装置
KR20030058703A (ko) * 2001-12-31 2003-07-07 엘지전자 주식회사 베어 칩의 인쇄 회로 기판 접속구조
US7215026B2 (en) * 2005-04-14 2007-05-08 Samsung Electonics Co., Ltd Semiconductor module and method of forming a semiconductor module
JP6623508B2 (ja) * 2014-09-30 2019-12-25 日亜化学工業株式会社 光源及びその製造方法、実装方法
JP6681716B2 (ja) * 2016-01-13 2020-04-15 セイコーインスツル株式会社 電子部品

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