KR970068409A - Tone generation circuit using a digital signal processing processor (DSP) - Google Patents

Tone generation circuit using a digital signal processing processor (DSP) Download PDF

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Publication number
KR970068409A
KR970068409A KR1019960009219A KR19960009219A KR970068409A KR 970068409 A KR970068409 A KR 970068409A KR 1019960009219 A KR1019960009219 A KR 1019960009219A KR 19960009219 A KR19960009219 A KR 19960009219A KR 970068409 A KR970068409 A KR 970068409A
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KR
South Korea
Prior art keywords
tone
tone data
address
digital signal
signal processing
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KR1019960009219A
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Korean (ko)
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KR0168795B1 (en
Inventor
이동주
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김광호
삼성전자 주식회사
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Priority to KR1019960009219A priority Critical patent/KR0168795B1/en
Publication of KR970068409A publication Critical patent/KR970068409A/en
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Publication of KR0168795B1 publication Critical patent/KR0168795B1/en

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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M19/00Current supply arrangements for telephone systems
    • H04M19/02Current supply arrangements for telephone systems providing ringing current or supervisory tones, e.g. dialling tone or busy tone
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M3/00Automatic or semi-automatic exchanges
    • H04M3/02Calling substations, e.g. by ringing

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Devices For Supply Of Signal Current (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. Technical field to which the invention described in the claims belongs

디지탈 신호 처리 프로세서를 사용하여 고속으로 톤신호를 발생하는 기술이다.It is a technology that generates a tone signal at high speed using a digital signal processing processor.

2. 발명이 해결하고자 하는 기술적 과제2. Technical Problems to be Solved by the Invention

톤의 증가에 따라 하드웨어 변경없이 다양한 톤신호를 고속으로 서비스하고, 회로를 간소화하는데 있다.As the tone increases, it is possible to service various tone signals at high speed and to simplify the circuit without changing the hardware.

3. 발명의 해결방법의 요지3. The point of the solution of the invention

프레임 싱크신호가 인가될 시 소정의 클럭신호에 의해 카운팅하여 순차적으로 반복되는 톤어드레스를 발생하는 디지탈신호처리수단과, 각종 톤신호에 대응하는 톤소오스, 즉 각 톤에 대한 톤데이타들을 모두 저장하고 있으며, 상기 디지탈신호처리수단으로부터 인가되는 톤어드레스에 해당하는 메모리 영역에 저장되어 있는 톤 데이타를 출력하는 불휘발성 메모리와, 프레임 싱크신호를 입력하여 채널 CH0-CH31에 해당하는 톤데이타를 순차적으로 독출하기 위한 어드레스를 발생하는 톤데이타 순차독출수단과, 상기 디지탈신호 처리수단으로부터 출력된 어드레스에 의해 상기 롬(14)로부터 읽어들인 톤데이타를 일시적으로 저장하고, 상기 저장된 데이타를 상기 톤데이타 순차독출수단으로부터 출력되는 어드레스에 의해 출력하는 휘발성메모리와, 상기 톤데이타 순차독출수단으로부터 채널 CH0-CH31에 해당하는 톤데이타를 순차적으로 독출하기 위한 어드레스가 인가될시 상기 휘발성 메모리로부터 독출된 병렬데이타를 직렬데이타로 변환하여 출력하는 병/직렬변환수단으로 구성한다.Digital signal processing means for counting a predetermined clock signal when a frame sync signal is applied and generating a tone address that is repeated in sequence and storing tone data corresponding to various tone signals, that is, tone data for each tone A nonvolatile memory for outputting tone data stored in a memory area corresponding to a tone address applied from the digital signal processing means and a nonvolatile memory for sequentially inputting tone data corresponding to the channels CH0 to CH31 by inputting a frame sync signal, A tone data sequential reading means for generating an address for outputting tone data, a tone data sequential reading means for temporarily storing the tone data read from the ROM 14 by the address output from the digital signal processing means, A volatile memory for outputting an address, Serial conversion means for converting parallel data read from the volatile memory into serial data when an address for sequentially reading the tone data corresponding to the channels CH0 to CH31 is applied from the tone data sequential reading means .

4. 발명의 중요한 용도4. Important Uses of the Invention

톤신호 발생회로에 적용한다.Tone signal generating circuit.

Description

디지탈 신호처리 프로세서(DSP)를 이용한 톤발생회로Tone generation circuit using a digital signal processing processor (DSP)

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도는 종래의 DSP를 이용한 톤발생회로도, 제2도는 제1도의 각부분에 대한 동작파형도, 제3도는 본 발명에 따른 톤발생 회로도, 제4도는 본 발명에 따른 각종 톤데이타 생성 제어 흐름도.FIG. 4 is a flowchart of various tone data generation control processes according to the present invention. FIG. 4 is a timing chart of a conventional tone generating circuit using a DSP, FIG. .

Claims (2)

디지탈 신호처리 프로세서를 이용한 톤발생회로에 있어서, 프레임 싱크신호가 인가될 시 소정의 클럭신호에 의해 카운팅하여 순차적으로 반복되는 톤어드레스를 발생하는 디지탈신호처리수단과, 각종 톤신호에 대응하는 톤소오스, 즉 각 톤에 대한 톤데이타들을 모두 저장하고 있으며, 상기 디지탈신호처리수단으로부터 인가되는 톤어드레스에 해당하는 메모리 영역에 저장되어 있는 톤데이타를 출력하는 불휘발성 메모리와, 프레임 싱크신호를 입력하여 채널 CH0-CH31에 해당하는 톤데이타를 순차적으로 독출하기 위한 어드레스를 발생하는 톤데이타 순차독출 수단과, 상기 디지탈신호 처리수단으로부터 출력된 어드레스에 의해 상기 롬(14)로부터 읽어들인 톤데이타를 일시적으로 저장하고, 상기 저장된 데이타를 상기 톤데이타 순차독출수단으로부터 출력되는 어드레스에 의해 출력하는 휘발성메모리와, 상기 톤데이타 순차독출수단으로부터 채널 CH0-CH31에 해당하는 톤데이타를 순차적으로 독출하기 위한 어드레스가 인가될 시 상기 휘발성 메모리로부터 독출된 병렬데이타를 직렬데이타로 변환하여 출력하는 병/직렬변환수단으로 구성함을 특징으로 하는 디지탈 신호 프로세서를 이용한 톤발생회로.A tone generating circuit using a digital signal processing processor, comprising: digital signal processing means for generating a tone address sequentially counted by a predetermined clock signal when a frame sync signal is applied; A nonvolatile memory for storing tone data for each tone and outputting tone data stored in a memory area corresponding to a tone address applied from the digital signal processing means; Tone data sequential reading means for generating an address for sequentially reading out tone data corresponding to CH0 to CH31, tone data read out means for temporarily storing tone data read from the ROM 14 by the address outputted from the digital signal processing means And stores the stored data in the tone data sequential reading means And outputting the parallel data read from the volatile memory when the address for sequentially reading the tone data corresponding to the channels CH0-CH31 is applied from the tone data sequential reading means to the serial data And converting the digital signal into a digital signal. 제1항에 있어서, 프레임 싱크신호와 2.048MHz클럭신호를 입력하여 상기 병/직렬변환수단의 로드신호를 발생하는 출력제어수단을 더 구비함을 특징으로 하는 디지탈신호 처리프로세서를 이용한 톤발생회로.The tone generation circuit according to claim 1, further comprising output control means for receiving a frame sync signal and a 2.048 MHz clock signal to generate a load signal of the parallel / serial conversion means. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960009219A 1996-03-29 1996-03-29 Tone generator using digital signal processor KR0168795B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960009219A KR0168795B1 (en) 1996-03-29 1996-03-29 Tone generator using digital signal processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960009219A KR0168795B1 (en) 1996-03-29 1996-03-29 Tone generator using digital signal processor

Publications (2)

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KR970068409A true KR970068409A (en) 1997-10-13
KR0168795B1 KR0168795B1 (en) 1999-02-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100428675B1 (en) * 1999-11-24 2004-04-30 엘지전자 주식회사 Apparatus for transmitting tone by using frequency processing option in electronic switch board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100428675B1 (en) * 1999-11-24 2004-04-30 엘지전자 주식회사 Apparatus for transmitting tone by using frequency processing option in electronic switch board

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Publication number Publication date
KR0168795B1 (en) 1999-02-01

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