KR970055812A - Interleaving Device for Personal Communication System - Google Patents

Interleaving Device for Personal Communication System Download PDF

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Publication number
KR970055812A
KR970055812A KR1019950070996A KR19950070996A KR970055812A KR 970055812 A KR970055812 A KR 970055812A KR 1019950070996 A KR1019950070996 A KR 1019950070996A KR 19950070996 A KR19950070996 A KR 19950070996A KR 970055812 A KR970055812 A KR 970055812A
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KR
South Korea
Prior art keywords
data
outputting
parallel
clock signal
predetermined clock
Prior art date
Application number
KR1019950070996A
Other languages
Korean (ko)
Other versions
KR100198211B1 (en
Inventor
곽재봉
Original Assignee
유기범
대우통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 유기범, 대우통신 주식회사 filed Critical 유기범
Priority to KR1019950070996A priority Critical patent/KR100198211B1/en
Publication of KR970055812A publication Critical patent/KR970055812A/en
Application granted granted Critical
Publication of KR100198211B1 publication Critical patent/KR100198211B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)

Abstract

본 발명은 개인통신 시스템에 있어서 기지국과 단말기 간의 데이터 송수신시에 송수신될 데이터를 인터리빙 처리함에 있어 456비트의 데이터를 심도 6으로 인터리빙하기 위한 개인통신 시스템용 인터리빙장치에 관한 것으로서, 456비트의 데이터를 입력함과 더불어 소정의 클록신호에 따라 그 입력된 데이터를 직렬로 출력하는 데이터입력수단과, 상기 데이터입력수단에서 출력되는 데이터를 8비트의 비트단위로 입력하는 병렬로 출력하는 시프트레지스터, 상기 시프트레지스터의 각 비트출력을 순차로 76비트 입력하고, 소정의 클록신호에 따라 이를 병렬로 출력하는 데이터시프트수단 및 상기 데이터시프트수단으로부터 출력되는 병렬데이터를 로드한 후 소정의 클록신호에 따라 이를 병렬로 출력하는 데이터출력수단을 포함하여 구성된 것을 특징으로 한다.The present invention relates to an interleaving apparatus for a personal communication system for interleaving 456 bits of data to a depth of 6 in interleaving data to be transmitted and received when transmitting and receiving data between a base station and a terminal in a personal communication system. A data input means for serially outputting the input data in accordance with a predetermined clock signal, and a shift register for outputting the data output from the data input means in 8-bit bit units in parallel; 76 bits are sequentially inputted to each bit output of the register, the data shifting means for outputting them in parallel according to a predetermined clock signal, and the parallel data outputted from the data shifting means are loaded and then parallelly outputted according to the predetermined clock signal. Characterized in that it comprises a data output means for outputting Shall be.

※ 대표도 : 제3도※ Representative diagram: 3rd

Description

개인통신 시스템용 인터리빙장치Interleaving Device for Personal Communication System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 1실시예에 따른 개인통신 시스템용 인터리빙장치를 나타낸 회로구성도.3 is a circuit diagram showing an interleaving apparatus for a personal communication system according to an embodiment of the present invention.

Claims (1)

456비트의 데이터를 입력함과 더불어 소정의 클록신호에 따라 그 입력된 데이터를 직렬로 출력하는 데이터입력수단과, 상기 데이터입력수단에서 출력되는 데이터를 8비트의 비트단위로 입력하는 병렬로 출력하는 시프트레지스터, 상기 시프트레지스터의 각 비트출력을 순차로 76비트 입력하고, 소정의 클록신호에 따라 이를 병렬로 출력하는 데이터시프트수단 및 상기 데이터시프트수단으로부터 출력되는 병렬데이터를 로드한 후 소정의 클록신호에 따라 이를 병렬로 출력하는 데이터출력수단을 포함하여 구성된 것을 특징으로 하는 개인통신 시스템용 인터리빙장치.Data input means for serially outputting 456 bits of data and outputting the input data in accordance with a predetermined clock signal, and outputting the data output from the data input means in parallel for inputting the data in 8 bit units. A shift register, and each bit output of the shift register are sequentially input 76 bits, and the data shift means for outputting them in parallel according to a predetermined clock signal, and the parallel data output from the data shift means is loaded and then the predetermined clock signal Interleaving apparatus for a personal communication system, characterized in that it comprises a data output means for outputting them in parallel. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950070996A 1995-12-30 1995-12-30 Interleaving device for pcs KR100198211B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950070996A KR100198211B1 (en) 1995-12-30 1995-12-30 Interleaving device for pcs

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950070996A KR100198211B1 (en) 1995-12-30 1995-12-30 Interleaving device for pcs

Publications (2)

Publication Number Publication Date
KR970055812A true KR970055812A (en) 1997-07-31
KR100198211B1 KR100198211B1 (en) 1999-06-15

Family

ID=19448799

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950070996A KR100198211B1 (en) 1995-12-30 1995-12-30 Interleaving device for pcs

Country Status (1)

Country Link
KR (1) KR100198211B1 (en)

Also Published As

Publication number Publication date
KR100198211B1 (en) 1999-06-15

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