KR970053650A - BLP package - Google Patents

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Publication number
KR970053650A
KR970053650A KR1019950048309A KR19950048309A KR970053650A KR 970053650 A KR970053650 A KR 970053650A KR 1019950048309 A KR1019950048309 A KR 1019950048309A KR 19950048309 A KR19950048309 A KR 19950048309A KR 970053650 A KR970053650 A KR 970053650A
Authority
KR
South Korea
Prior art keywords
chip
bus board
attached
package
pad
Prior art date
Application number
KR1019950048309A
Other languages
Korean (ko)
Other versions
KR0167281B1 (en
Inventor
전동석
Original Assignee
문정환
Lg 반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, Lg 반도체주식회사 filed Critical 문정환
Priority to KR1019950048309A priority Critical patent/KR0167281B1/en
Publication of KR970053650A publication Critical patent/KR970053650A/en
Application granted granted Critical
Publication of KR0167281B1 publication Critical patent/KR0167281B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 비엘피 패키지에 관한 것으로, 종래의 패키지가 규격화된 리드구성때문에 칩의 본드패드의 설계자유도가 떨어지는 등의 문제점이 있어 이를 해결하기 위한 것이다. 이와 같은 본 발명은 히트싱크(12)의 상면에 부착되는 칩(11)과, 상기 히트싱크(12)상의 칩(11)주변부에 부착되어 칩(11)과 인너리드(17)의 전기적인 연결을 수행하는 버스보드(20)와, 상기 버스보드(20)의 외주부 가장자리가 부착되고 버스보드(20)와의 전기적인 연결을 위한 와이어(15)가 본딩되는 인너리드(17)가 구비된 리드프레임(16)으로 구성되어 이들 구성요소가 몰딩컴파운드로 일정 면적 몰딩되어 패키지몸체(10')를 이루도록 된다. 이와 같은 본 발명에 의하면 패키지에 사용되는 칩의 패드설계 자유도가 높아지고 따라서 다핀이 요구되는 제품이나 높은 파워가 요구되는 제품의 설 제가 용이하게 되는 이점이 있다.The present invention relates to a BLP package, and to solve this problem, there is a problem that the design freedom of the bond pad of the chip is reduced due to the lead structure of the conventional package. The present invention as described above is attached to the chip 11 is attached to the upper surface of the heat sink 12, the chip 11 on the heat sink 12 is attached to the electrical connection between the chip 11 and the inner lead 17 The lead frame is provided with an inner lead 17 to which the bus board 20 performing the step and the outer circumferential edge of the bus board 20 are attached and the wire 15 for bonding the bus board 20 are bonded. It is composed of (16) these components are molded in a predetermined area with a molding compound to form a package body (10 '). According to the present invention as described above, there is an advantage in that the pad design freedom of the chip used in the package is increased, and thus, the installation of a product requiring high pins or a product requiring high power can be easily performed.

Description

비엘피 패키지BLP package

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 비엘피 패키지의 구조를 도시한 단면도.2 is a cross-sectional view showing the structure of the BLP package according to the present invention.

Claims (3)

히트싱크의 상면에 부착되어 있는 칩과, 상기 히트싱크상의 칩주변부에 부착되어 칩과 인너리드의 전기적인 연결을 수행하는 버스보드와, 상기 버스보드의 외주부 가장자리가 부착되고 버스보드와의 전기적인 연결을 위한 와이어가 본딩되는 인너리드가 구비된 리드프레임으로 구성되어 이들 구성요소가 몰딩컴파운드로 일정면적 몰딩되어 패키지몸체를 이룸을 특징으로 하는 비엘피 패키지.A chip attached to the top surface of the heat sink, a bus board attached to the chip peripheral portion on the heat sink to perform electrical connection between the chip and the inner lead, and an outer peripheral edge of the bus board is attached and electrically connected to the bus board. A BLP package comprising a lead frame having an inner lead to which wires for bonding are bonded, and these components are molded in a predetermined area with a molding compound to form a package body. 제1항에 있어서, 상기 버스보드는 상기 칩의 패드와의 와이어 연결을 위한 입력패드가 칩의 패드와 인접되는 부위에 형성되고, 리드프레임의 인너리드와의 와이어 연결을 위한 출력패드가 가장자리 둘레에 형성되며, 상기 입력패드와 출력패드를 연결하는 배선부가 구비되어 구성됨을 특징으로 하는 비엘피 패키지.The bus board of claim 1, wherein an input pad for wire connection with the pad of the chip is formed at a portion adjacent to the pad of the chip, and an output pad for wire connection with an inner lead of the lead frame is formed around an edge. Is formed in, the BLP package, characterized in that configured to be provided with a wiring portion for connecting the input pad and the output pad. 제2항에 있어서, 상기 버스보드는 중앙에 상기 칩이 위치되는 장방형의 통공이 형성된 장방형의 판상으로 형성됨을 특징으로 하는 비엘피 패키지.The BLP package according to claim 2, wherein the bus board is formed in a rectangular plate shape having a rectangular through hole formed at the center thereof. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950048309A 1995-12-11 1995-12-11 Blp package KR0167281B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950048309A KR0167281B1 (en) 1995-12-11 1995-12-11 Blp package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950048309A KR0167281B1 (en) 1995-12-11 1995-12-11 Blp package

Publications (2)

Publication Number Publication Date
KR970053650A true KR970053650A (en) 1997-07-31
KR0167281B1 KR0167281B1 (en) 1998-12-15

Family

ID=19438999

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950048309A KR0167281B1 (en) 1995-12-11 1995-12-11 Blp package

Country Status (1)

Country Link
KR (1) KR0167281B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100585585B1 (en) * 1999-07-05 2006-06-07 삼성테크윈 주식회사 Semiconductor package

Also Published As

Publication number Publication date
KR0167281B1 (en) 1998-12-15

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