KR970053577A - Method for forming contact hole buried metal wiring in semiconductor device - Google Patents

Method for forming contact hole buried metal wiring in semiconductor device Download PDF

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Publication number
KR970053577A
KR970053577A KR1019950069500A KR19950069500A KR970053577A KR 970053577 A KR970053577 A KR 970053577A KR 1019950069500 A KR1019950069500 A KR 1019950069500A KR 19950069500 A KR19950069500 A KR 19950069500A KR 970053577 A KR970053577 A KR 970053577A
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South Korea
Prior art keywords
contact hole
forming
film
depositing
metal film
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KR1019950069500A
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Korean (ko)
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KR100186985B1 (en
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조경수
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김주용
현대전자산업 주식회사
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Priority to KR1019950069500A priority Critical patent/KR100186985B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

본 발명은 반도체 소자의 제조방법에 관한 것으로서, 특히 직경이 큰 콘택홀을 매립하는 콘택홀 매립 금속배선 형성방법을 제공하기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to provide a method for forming a contact hole-embedded metal wiring to fill a contact hole having a large diameter.

이와같은 목적을 달성하기 위한 금속배선 형성 방법은 반도체 기판에 형성된 산화막의 소정 영역에 최종 콘택홀의 직경보다 작은 제1콘택홀을 형성하는 단계; 제1콘택홀에 텅스텐 플러그를 형성하는 단계; 제1콘택홀에 매립된 텅스텐 플러그의 소정부분과 산화막의 소정부분을 포함하는 영역을 노출시키는 감광막 마스크 패턴을 형성하는 단계; 감광막 마스크와 노출된 텅스텐 플러그를 식각 장벽으로 하여 노출된 산화막에 제2콘택홀을 형성하는 단계; 제2 콘택홀을 포함한 전면에 금속막을 매립하여 제2금속배선을 형성하는 것을 특징으로 한다.The metallization method for achieving the above object comprises the steps of forming a first contact hole smaller than the diameter of the final contact hole in a predetermined region of the oxide film formed on the semiconductor substrate; Forming a tungsten plug in the first contact hole; Forming a photoresist mask pattern exposing a region including a predetermined portion of the tungsten plug embedded in the first contact hole and a predetermined portion of the oxide film; Forming a second contact hole in the exposed oxide film using the photoresist mask and the exposed tungsten plug as an etch barrier; A second metal wiring is formed by embedding a metal film on the entire surface including the second contact hole.

Description

반도체 소자의 콘택홀 매립 금속배선 형성방법Method for forming contact hole buried metal wiring in semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 일실시 예에 따른 반도체 소자의 콘택홀 매립시의 금속배선 형성방법을 설명하기 위한 공정 흐름도.1 is a process flowchart illustrating a method for forming metal wirings when a contact hole is embedded in a semiconductor device according to an embodiment of the present disclosure.

Claims (11)

반도체 기판에 형성된 전도영역을 절연시키기 위한 산화막의 소정 영역에 사진식각법으로 최종 콘택홀의 직경보다 작은 제1콘택홀을 형성하는 단계; 상기 제1콘택홀의 형상을 유지할 정도의 얇은 두께로 고융점 금속의 장벽 금속막을 상기 제1콘택홀을 포함한 전면에 증착하는 단계; 소정 온도 및 소정시간동안 제1열처리 하는 단계; 상기 장벽 금속막 전면에 상기 제1콘택홀을 충분히 매립할 정도의 소정 두께로 텅스텐 금속막을 증착하는 단계; 상기 산화막의 표면이 노출될 때까지 증착된 텅스텐 금속막을 전면 식각하는 단계; 상기 제1콘택홀에 매립된 텅스텐 플러그의 소정부분과 산화막의 소정부분을 포함하는 영역을 노출시키는 감광막 마스크 패턴을 형성하는 단계; 상기 감광막 마스크와 노출된 텅스텐 플러그를 식각 장벽으로 하여 노출된 산화막에 제2콘택홀을 형성하는 단계; 상기 제2콘택홀을 포함한 전면에 상기 제2콘택홀의 형성하는 단계 ; 상기 제2콘택홀을 포함한 전면에 상기 제2콘택홀의 형상을 유지하는 정도의 얇은 두께로 고융점 금속의 장벽 금속막을 증착하는 단계; 소정온도와 소정시간동안 제2열처리하는 단계; 전면에 상기 제2콘택홀을 매립할 정도의 소정 두께로 텅스텐 금속막을 증착하는 단계; 전면에 제1, 제2 콘택홀 부분과 접촉하는 제2금속배선을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 콘택홀 매립금속배선 형성 방법.Forming a first contact hole smaller than the diameter of the final contact hole by a photolithography method in a predetermined region of the oxide film for insulating the conductive region formed on the semiconductor substrate; Depositing a barrier metal film of a high melting point metal on the entire surface including the first contact hole to a thickness thin enough to maintain the shape of the first contact hole; Performing a first heat treatment for a predetermined temperature and for a predetermined time; Depositing a tungsten metal film to a predetermined thickness such that the first contact hole is sufficiently buried in the entire barrier metal film; Etching an entire surface of the deposited tungsten metal film until the surface of the oxide film is exposed; Forming a photoresist mask pattern exposing a region including a predetermined portion of the tungsten plug embedded in the first contact hole and a predetermined portion of the oxide film; Forming a second contact hole in the exposed oxide film using the photoresist mask and the exposed tungsten plug as an etch barrier; Forming the second contact hole on a front surface of the second contact hole; Depositing a barrier metal film of a high melting point metal on a front surface including the second contact hole to a thickness thin enough to maintain the shape of the second contact hole; Performing a second heat treatment for a predetermined temperature and for a predetermined time; Depositing a tungsten metal film to a predetermined thickness such that the second contact hole is buried in the entire surface; Forming a second metal wiring in contact with the first and second contact hole portions on the front surface thereof. 제1항에 있어서, 상기 제2금속배선 형성단계는 제2콘택홀을 매립한 텅스텐 금속막 위에 알루미늄 합금막을 소정 두께로 증착하는 단계; 알루미늄 합금막의 전면에 반사방지막을 소정 두께로 증착하는 단계; 전면에 감광막 마스크 패턴을 형성하여 제2금속배선을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 콘택홀 매립 금속배선 형성 방법.The method of claim 1, wherein the forming of the second metal wiring comprises: depositing an aluminum alloy film to a predetermined thickness on the tungsten metal film having the second contact hole; Depositing an antireflection film on a front surface of the aluminum alloy film to a predetermined thickness; Forming a second metal wiring by forming a photoresist mask pattern on the entire surface of the contact hole; 제1항에 있어서, 상기 제2금속배선 형성단계는 제2콘택홀을 매립한 텅스텐 금속막을 산화막의 표면이 노출될 때까지 전면식각하는 단계; 식각된 전면에 고융점 장벽 금속막을 소정 두께로 증착하는 단계; 소정 온도 및 소정 시간동안 열처리 하는 단계; 알루미늄 합금막을 전면에 증착하는 단계; 알루미늄 합금막의 전면에 반사방지막을 소정 두께로 증착하는 단계; 전면에 감광막 마스크 패턴을 형성하여 제2금속배선을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 콘택홀 매립 금속배선 형성 방법.The method of claim 1, wherein the forming of the second metal wiring comprises: etching the tungsten metal film with the second contact hole until the surface of the oxide film is exposed; Depositing a high melting point barrier metal film on the etched front surface to a predetermined thickness; Heat treatment for a predetermined temperature and for a predetermined time; Depositing an aluminum alloy film on the entire surface; Depositing an antireflection film on a front surface of the aluminum alloy film to a predetermined thickness; Forming a second metal wiring by forming a photoresist mask pattern on the entire surface of the contact hole; 제3항에 있어서, 상기 장벽 금속막은 티타늄나이트라이드인 것을 특징으로 하는 반도체 소자의 콘택홀 매립 금속배선 형성 방법.4. The method of claim 3, wherein the barrier metal film is titanium nitride. 제3항에 있어서, 상기 장벽 금속막은 티타늄나이트라이드와 상기 티타늄나이트라이드 위의 고융점 금속막의 적층구조로 형성하는 것을 특징으로 하는 반도체 소자의 콘택홀 매립 금속배선 형성 방법.4. The method of claim 3, wherein the barrier metal film is formed in a stacked structure of titanium nitride and a high melting point metal film on the titanium nitride. 제5항에 있어서, 상기 고융점 금속막은 티타늄, 몰리브듐, 티타늄텅스텐, 탄탈륨막 중에서 선택적으로 형성하는 것을 특징으로 하는 반도체 소자의 콘택홀 매립 금속배선 형성 방법.The method of claim 5, wherein the high melting point metal film is selectively formed from a titanium, molybdium, titanium tungsten, or tantalum film. 제3항에 있어서, 상기 열처리 단계는 튜브형 로에서 400℃이상의 온도와 10분이상의 시간 동안 진행하는 것을 특징으로 하는 반도체 소자의 콘택홀 매립 금속배선 형성 방법.The method of claim 3, wherein the heat treatment is performed in a tubular furnace at a temperature of 400 ° C. or more and for at least 10 minutes. 5. 제1항에 있어서, 상기 장벽 금속막은 하부의 티타늄막과 상기 티타늄막 상의 티타늄나이트라이드의 적층구조로 형성하는 것을 특징으로 하는 반도체 소자의 콘택홀 매립 금속배선 형성 방법.The method of claim 1, wherein the barrier metal layer is formed of a stacked structure of a titanium layer below and a titanium nitride layer on the titanium layer. 제1항에 있어서, 상기 제1, 제2 열처리 단계는 튜브형 로에서 400℃이상의 온도와 10분 이상의 시간동안 진행하는 것을 특징으로 하는 반도체 소자의 콘택홀 매립 금속배선 형성 방법.The method of claim 1, wherein the first and second heat treatment steps are performed in a tubular furnace at a temperature of 400 ° C. or more for 10 minutes or more. 제1항에 있어서, 상기 고융점 금속막은 Ti, TiN, Mo, Co, Ta중에서 서로 다른 재질을 선택하는 것을 특징으로 하는 반도체 소자의 콘택홀 매립 금속배선 형성 방법.The method of claim 1, wherein the high melting point metal layer is formed of a material selected from among Ti, TiN, Mo, Co, and Ta. 제1항에 있어서, 상기 산화막 표면을 노출시키기 위한 식각은 화학 및 기계적 연마법을 실시하는 것을 특징으로 하는 반도체 소자의 콘택홀 매립 금속배선 형성 방법.The method of claim 1, wherein etching for exposing the surface of the oxide layer is performed by chemical and mechanical polishing methods. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950069500A 1995-12-30 1995-12-30 Manufacture of semiconductor device KR100186985B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000042860A (en) * 1998-12-28 2000-07-15 김영환 Method for forming metal wiring of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000042860A (en) * 1998-12-28 2000-07-15 김영환 Method for forming metal wiring of semiconductor device

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