KR970053437A - Device isolation film formation method using trench - Google Patents

Device isolation film formation method using trench Download PDF

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Publication number
KR970053437A
KR970053437A KR1019950058887A KR19950058887A KR970053437A KR 970053437 A KR970053437 A KR 970053437A KR 1019950058887 A KR1019950058887 A KR 1019950058887A KR 19950058887 A KR19950058887 A KR 19950058887A KR 970053437 A KR970053437 A KR 970053437A
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KR
South Korea
Prior art keywords
device isolation
trench
layer
forming
region
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KR1019950058887A
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Korean (ko)
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KR100198620B1 (en
Inventor
강상우
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문정환
Lg 반도체주식회사
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Priority to KR1019950058887A priority Critical patent/KR100198620B1/en
Publication of KR970053437A publication Critical patent/KR970053437A/en
Application granted granted Critical
Publication of KR100198620B1 publication Critical patent/KR100198620B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 DRAM 셀의 소자 격리막 형성공정에 관한 것으로, 반도체 기판에 제1 산화막, 질화막을 차례로 증착하고, 상기 질화막층을 포토리소그래피 공정으로 선택적으로 제거하여 소자격리 영역을 정의하는 공정과, 상기 질화막층이 제거된 소자격리 영역의 반도체 기판에 건식각(Dry Etch)으로 트랜치를 형성하는 공정과, 전면에 제2 산화막을 증착하고 에치백 하여 트렌치 측면에 측벽을 형성하는 공정과, 상기 측벽이 형성된 트렌치 하부영역을 습식식각으로 넓혀 충분한 소자격리 영역을 확보하는 공정과, 상기 확장된 트렌치 하부영역에 열산화막을 성장시키고, 상기 트렌치 영역을 포함하는 전면에 충분히 두꺼운 제3 산화막층을 형성하는 공정과, 상기 제3 산화막층은 활성영역에 남아 있는 질화막과 동일 높이로 식각한 후, 상기 질화막을 제거하는 공정과, 상기 반도체 기판의 표면에 돌출되어 있는 제1, 2, 3 산화막을 에치백 하여 소자 격리층을 형성하는 공정으로 이루어져 격리 산화막의 버즈빅 현상을 막고, 누설전류를 효율적으로 제어할 수 있는 트렌치를 이용한 소자 격리막 형성방법에 관한 것이다.The present invention relates to a device isolation film forming process of a DRAM cell, comprising: depositing a first oxide film and a nitride film on a semiconductor substrate in order, and selectively removing the nitride film layer by a photolithography process to define a device isolation region; Forming a trench by dry etching on the semiconductor substrate of the device isolation region from which the layer is removed, forming a sidewall on the side of the trench by depositing and etching back a second oxide layer on the front surface, and forming the sidewall Widening the trench lower region by wet etching to secure a sufficient device isolation region; growing a thermal oxide film in the extended trench lower region; and forming a sufficiently thick third oxide layer on the entire surface including the trench region; The third oxide layer is etched at the same height as the nitride layer remaining in the active region, and then the nitride layer is removed. And forming a device isolation layer by etching back the first, second and third oxide films protruding from the surface of the semiconductor substrate, thereby preventing the buzzing phenomenon of the isolation oxide film and efficiently controlling the leakage current. It relates to a device isolation film forming method using.

Description

트렌치를 이용한 소자 격리막 형성방법Device isolation film formation method using trench

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도 (a) 내지 (k)는 본 발명의 소자 격리층 형성을 위한 공정단면도.2 (a) to (k) are process cross-sectional views for forming a device isolation layer of the present invention.

Claims (1)

반도체 기판에 제1 산화막, 질화막을 차례로 증착하고, 상기 질화막층을 포토리소그래피 공정으로 선택적으로 제거하여 소자격리 영역을 정의하는 공정과, 상기 질화막층이 제거된 소자격리 영역의 반도체 기판에 건식각(Dry Etch)으로 트렌치를 형성하는 공정과, 전면에 제2 산화막을 증착하고 에치백 하여 트렌치 측면에 측벽을 형성하는 공정과, 상기 측벽이 형성된 트렌치 하부영역을 습식식각으로 넓혀 충분한 소자격리 영역을 확보하는 공정과, 상기 확장된 트렌치 하부영역에 열산화막을 성장시키고, 상기 트렌치 영역을 포함하는 전면에 충분히 두꺼운 제3 산화막층을 형성하는 공정과, 상기 제3 산화막층은 활성영역에 남아 있는 질화막과 동일 높이로 식각한 후, 상기 질화막을 제거하는 공정과, 상기 반도체 기판의 표면에 돌출되어 있는 제1, 2, 3 산화막을 에치백 하여 소자 격리층을 형성하는 공정을 포함하여 이루어짐을 특징으로 하는 트렌치를 이용한 소자 격리막 형성방법.Depositing a first oxide film and a nitride film on the semiconductor substrate in order, and selectively removing the nitride film layer by a photolithography process to define a device isolation region; and dry etching the semiconductor substrate of the device isolation region from which the nitride film layer has been removed. Dry etching), depositing a second oxide layer on the entire surface, and etching back to form sidewalls on the sidewalls of the trench, and wet-etching the trench lower regions where the sidewalls are formed to secure sufficient device isolation regions. Growing a thermal oxide film in the extended trench lower region, and forming a sufficiently thick third oxide film on the entire surface including the trench region; and the third oxide layer comprises a nitride film remaining in the active region; After etching to the same height, removing the nitride film; and first, second, and third protrusions protruding from the surface of the semiconductor substrate. A method of forming a device isolation film using a trench, comprising: etching back an oxide film to form a device isolation layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950058887A 1995-12-27 1995-12-27 Manufacturing method of isolation film using trench KR100198620B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950058887A KR100198620B1 (en) 1995-12-27 1995-12-27 Manufacturing method of isolation film using trench

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950058887A KR100198620B1 (en) 1995-12-27 1995-12-27 Manufacturing method of isolation film using trench

Publications (2)

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KR970053437A true KR970053437A (en) 1997-07-31
KR100198620B1 KR100198620B1 (en) 1999-06-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100319625B1 (en) * 1999-05-28 2002-01-05 김영환 Fabricating method of semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990073644A (en) * 1998-03-02 1999-10-05 김영환 Manufacturing Method of Semiconductor Device
KR100469763B1 (en) * 2003-02-03 2005-02-02 매그나칩 반도체 유한회사 Method for forming isolation of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100319625B1 (en) * 1999-05-28 2002-01-05 김영환 Fabricating method of semiconductor device

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