KR970053092A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
KR970053092A
KR970053092A KR1019950066152A KR19950066152A KR970053092A KR 970053092 A KR970053092 A KR 970053092A KR 1019950066152 A KR1019950066152 A KR 1019950066152A KR 19950066152 A KR19950066152 A KR 19950066152A KR 970053092 A KR970053092 A KR 970053092A
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South Korea
Prior art keywords
layer
forming
type
barrier metal
semiconductor device
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KR1019950066152A
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Korean (ko)
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KR100252543B1 (en
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임재은
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김주용
현대전자산업 주식회사
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Priority to KR1019950066152A priority Critical patent/KR100252543B1/en
Publication of KR970053092A publication Critical patent/KR970053092A/en
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Publication of KR100252543B1 publication Critical patent/KR100252543B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체 소자의 제조방법에 관한 것으로서, CMOS FET등과 같은 이중 게이트전극을 구비하는 반도체소자에서 P+ 폴리사이드 구조의 P+ 게이트전극의 다결정실리콘층과 금속실리사이드막의 사이에 TiN 장벽금속층을 개재시켜 금속실리사이드막을 통한 불순물의 확산 통로를 제거하여 게이트 산화막 손상에 따른 불량 발생을 방지하였으므로, 문턱전압 변화가 방지되고, 게이트 산화막의 열화를 방지하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein in a semiconductor device having a double gate electrode such as a CMOS FET, a metal is formed by interposing a TiN barrier metal layer between a polysilicon layer of a P + gate electrode having a P + polyside structure and a metal silicide layer. Since defects caused by damage to the gate oxide film are prevented by removing the diffusion path of impurities through the silicide layer, the threshold voltage is prevented and the degradation of the gate oxide film is prevented, thereby improving process yield and device operation reliability.

Description

반도체소자의 제조방법Manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1a도 내지 제1d도는 본 발명에 따른 반도체소자의 제조공정도.1A to 1D are manufacturing process diagrams of a semiconductor device according to the present invention.

Claims (5)

N형 반도체기판상에 게이트 산화막을 형성하는 공정과, 상기 게이트 산화막상에 P형 다결정실리콘층을 형성하는 공정과, 상기 다결정실리콘층상에 장벽금속층을 형성하는 공정과, 상기 장벽금속층상에 금속실리사이드막을 형성하는 공정과, 상기 금속실리사이드막에서 다결정실리콘층까지를 순차적으로 패턴닝하여 금속실리사이드막과 장벽금속층 및 다결정실리콘층 패턴으로된 게이트전극을 형성하는 공정을 구비함에 있다.Forming a gate oxide film on an N-type semiconductor substrate, forming a P-type polycrystalline silicon layer on the gate oxide film, forming a barrier metal layer on the polysilicon layer, and metal silicide on the barrier metal layer And forming a gate electrode having a metal silicide film, a barrier metal layer, and a polysilicon layer pattern by sequentially patterning the film from the metal silicide film to the polycrystalline silicon layer. 제1항에 있어서, 상기 장벽금속층이 TiN으로 형성되어 있는 것을 특징으로 하는 반도체소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein said barrier metal layer is formed of TiN. 제1항에 있어서, 상기 장벽금속층이 50∼200Å 두께로 형성되어 있는 것을 특징으로 하는 반도체소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the barrier metal layer is formed to have a thickness of 50 to 200 Å. 제1항에 있어서, 상기 금속실리사이드막이 W-실리사이드로 형성되어 있는 것을 특징으로 하는 반도체소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the metal silicide film is formed of W-silicide. 반도체기판 상의 일측 및 타측에 N웰 및 P웰을 형성하는 공정과, 상기 반도체기판에서 소자분리 영역으로 예정되어 있는 부분상에 소자분리 산화막을 형성하는 공정과, 상기 구조의 전표면에 게이트 산화막을 형성하는 공정과, 상기 구조의 전표면에 다결정실리콘층을 형성하는 공정과, 상기 N 및 P웰 상의 다결정실리콘층을 각각 P 및 N형 불순물을 주입하는 공정과, 상기 N형 다결정실리콘층상에 금속실리사이드막을 형성하는 공정과, 상기 금속실리사이드막과 P형 다결정실리콘층상에 장벽금속층을 형성하는 공정과, 상기 P형 다결정실리콘층 상부의 장벽금속층상에 금속실리사이드막을 형성하는 공정과, 상기 금속실리사이드막과 장벽금속층 및 P형 다결정실리콘층을 패턴닝하여 P형 게이트전극을 형성하고, 장벽금속층과 금속실리사이드막 및 N형 다결정실리콘층을 패터닝하여 N형 게이트전극을 형성하는 공정을 구비하는 반도체소자의 제조방법.Forming an N well and a P well on one side and the other side of the semiconductor substrate, forming an isolation layer on a portion of the semiconductor substrate that is intended as an isolation region, and forming a gate oxide layer on the entire surface of the structure Forming a layer, forming a polysilicon layer on the entire surface of the structure, injecting P and N type impurities into the polycrystalline silicon layer on the N and P wells, respectively, and forming a metal on the N type polycrystalline silicon layer. Forming a silicide film, forming a barrier metal layer on the metal silicide film and the P-type polysilicon layer, forming a metal silicide film on the barrier metal layer on the P-type polysilicon layer, and the metal silicide film The barrier metal layer and the P-type polysilicon layer are patterned to form a P-type gate electrode, and the barrier metal layer, the metal silicide film, and the N-type polysilicon layer A method of manufacturing a semiconductor device comprising the step of forming an N-type gate electrode by patterning a crystalline silicon layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950066152A 1995-12-29 1995-12-29 Method for manufacturing semiconductor device KR100252543B1 (en)

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KR100252543B1 KR100252543B1 (en) 2000-04-15

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Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6165470A (en) * 1984-09-07 1986-04-04 Hitachi Ltd Semiconductor ic device
JPS6254467A (en) * 1985-09-02 1987-03-10 Seiko Epson Corp Semiconductor device
JPH0194664A (en) * 1987-10-05 1989-04-13 Nec Corp Field-effect transistor

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