KR970052216A - Contact hole formation method of semiconductor device - Google Patents
Contact hole formation method of semiconductor device Download PDFInfo
- Publication number
- KR970052216A KR970052216A KR1019950048295A KR19950048295A KR970052216A KR 970052216 A KR970052216 A KR 970052216A KR 1019950048295 A KR1019950048295 A KR 1019950048295A KR 19950048295 A KR19950048295 A KR 19950048295A KR 970052216 A KR970052216 A KR 970052216A
- Authority
- KR
- South Korea
- Prior art keywords
- contact hole
- forming
- silicon oxide
- photoresist pattern
- semiconductor device
- Prior art date
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- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명의 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 특히 건식 식각에 의한 반도체 소자의 콘택홀 형성 방법에 관한 것이다.The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device by dry etching.
이와 같은 본 발명의 콘택홀 형성 방법은 실리콘 기판상에 실리콘 산화막을 형성하는 단계; 실리콘 산화막상에 콘택홀을 형성할 영역에 감광막 패턴을 형성하는 단계; 감광막 패턴이 형성된 실리콘 기판을 반응성 이온 챔버 내에 배치하고 고주파전원과 식가 가스 CHF3/CIF3을 공급하여 감광막 패턴의 형태로 실리콘 산화막을 식각하는 단계; 및 실리콘 산화막 식각시 손상된 실리콘층을 제거하는 단계를 포함하는 것을 특징으로 한다.Such a contact hole forming method of the present invention comprises the steps of forming a silicon oxide film on a silicon substrate; Forming a photoresist pattern on a region where a contact hole is to be formed on the silicon oxide film; Placing the silicon substrate on which the photoresist pattern is formed in a reactive ion chamber, and supplying a high frequency power source and a dietary gas CHF 3 / CIF 3 to etch the silicon oxide layer in the form of a photoresist pattern; And removing the damaged silicon layer when the silicon oxide layer is etched.
실리콘 산화막 식각시 기존의 CF4가스 대신 폴리머 생성을 억제할 수 있는 CIF3를 사용하는 것이 이 발명의 주된 요지이다.The use of CIF 3 , which can suppress the formation of polymers instead of the conventional CF 4 gas, is the main focus of the present invention.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제3도는 본 발명의 실시예에 따른 반도체 소자의 콘택홀 형성을 위한 건식 식각시의 챔버 내의 상태도.3 is a state diagram in a chamber during dry etching for forming a contact hole in a semiconductor device according to an embodiment of the present invention.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950048295A KR970052216A (en) | 1995-12-11 | 1995-12-11 | Contact hole formation method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950048295A KR970052216A (en) | 1995-12-11 | 1995-12-11 | Contact hole formation method of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970052216A true KR970052216A (en) | 1997-07-29 |
Family
ID=66593978
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950048295A KR970052216A (en) | 1995-12-11 | 1995-12-11 | Contact hole formation method of semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970052216A (en) |
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1995
- 1995-12-11 KR KR1019950048295A patent/KR970052216A/en not_active Application Discontinuation
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