KR970030927A - Manufacturing Method of Thin Film Transistor - Google Patents

Manufacturing Method of Thin Film Transistor Download PDF

Info

Publication number
KR970030927A
KR970030927A KR1019950044897A KR19950044897A KR970030927A KR 970030927 A KR970030927 A KR 970030927A KR 1019950044897 A KR1019950044897 A KR 1019950044897A KR 19950044897 A KR19950044897 A KR 19950044897A KR 970030927 A KR970030927 A KR 970030927A
Authority
KR
South Korea
Prior art keywords
manufacturing
thin film
insulating layer
entire surface
active layer
Prior art date
Application number
KR1019950044897A
Other languages
Korean (ko)
Other versions
KR100195265B1 (en
Inventor
윤찬주
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950044897A priority Critical patent/KR100195265B1/en
Publication of KR970030927A publication Critical patent/KR970030927A/en
Application granted granted Critical
Publication of KR100195265B1 publication Critical patent/KR100195265B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Optics & Photonics (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Thin Film Transistor (AREA)

Abstract

반도체 소자의 제조에 있어서, 특히 전기적 특성이 개선된 박막 트랜지스터(Thin Film Transistor, "TFT" 라고도 약함)를 제조하는 방법에 대해 기재되어 있다. 상기 박막 트랜지스터는 기판 상에 순차적으로 적층되어 있는 활성층과 제1절연층막 상에 게이트 전극을 형성하는 단계, 상기 게이트 전극에 의해 노출된 상기 제1절연층을 통하여 상기 활성층에 불순물을 도핑시켜 트랜지스터의 소오스 및 드레인 영역을 형성하는 단계, 상기 결과물의 전면에 제2절연층을 형성하는 단계 및 상기 소오스 및 드레인 영역에 도핑된 불순물을 활성화하는 단계를 포함하는 공정에 의하여 제조된다. 상기 방법에 의해 제조된 박막 트랜지스터는 박막 구조의 활성 영역에 도핑된 불순물이 공정 진행중에 수평 확산되어 초래되는 반도체 소자의 특성 악화를 방지할 수 있다.BACKGROUND OF THE INVENTION In the manufacture of semiconductor devices, a method of manufacturing thin film transistors (also referred to as thin film transistors), which have improved electrical properties, is described. The thin film transistor may include forming a gate electrode on an active layer and a first insulating layer film sequentially stacked on a substrate, and doping impurities into the active layer through the first insulating layer exposed by the gate electrode. Forming a source and drain region, forming a second insulating layer on the entire surface of the resultant, and activating impurities doped in the source and drain regions. The thin film transistor manufactured by the above method can prevent deterioration of characteristics of the semiconductor device caused by horizontal diffusion of impurities doped in the active region of the thin film structure during the process.

Description

박막 트랜지스터의 제조 방법Manufacturing Method of Thin Film Transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제5도 내지 제9도는 본 발명에 의한 일 실시예를 설명하기 위하여 순차적으로 도시한 단면도들이다.5 to 9 are cross-sectional views sequentially shown to explain an embodiment of the present invention.

Claims (9)

박막 트랜지스터를 제조하는 방법에 있어서, 기판 상에 순차적으로 적층되어 있는 활성층 및 게이트 산화막 상에 게이트 전극을 형성시키는 제1단계; 상기 게이트 전극을 불순물 도핑 방지 마스크로하여 상기 활성층에 불순물을 도핑시킴으로써 트랜지스터의 소오스 영역 및 드레인 영역을 형성하는 제2단계; 상기 결과물의 전면 상에 층간 절연막을 도포하는 제3단계; 및 상기 소오스 영역 및 드레인 영역에 도핑되어 있는 불순물을 활성화하는 제4단계를 포함하는 것을 특징으로 하는 TFT의 제조 방법.A method of manufacturing a thin film transistor, comprising: a first step of forming a gate electrode on an active layer and a gate oxide layer sequentially stacked on a substrate; A second step of forming a source region and a drain region of the transistor by doping the active layer with the gate electrode as an impurity doping mask; A third step of applying an interlayer insulating film on the entire surface of the resultant product; And a fourth step of activating the impurities doped in the source region and the drain region. 제1항에 있어서, 상기 제2단계에서 활성층에 불순물을 도핑하는 것은 이온 주입(Ion Implantation) 방법으로 진행하는 것을 특징으로 하는 TFT의 제조방법.The method of claim 1, wherein the doping of the impurity into the active layer in the second step is performed by an ion implantation method. 제1항에 있어서, 상기 제2단계에서 활성층에 불순물을 도핑하는 것은 이온 샤우어(Ion Shower) 방법으로 진행하는 것을 특징으로 하는 TFT의 제조방법.The method of claim 1, wherein the doping of the active layer with the impurity in the second step is performed by an ion shower method. 제1항에 있어서, 상기 제4단계에서 상기 층간 절연막은 실리콘 옥사이드(SiO2) 및 실리콘 나이트라이드(Si3N4)중 어느 하나의 물질로 이루어진 것을 특징으로 하는 TFT의 제조 방법.The method of claim 1, wherein the interlayer insulating layer is formed of any one of silicon oxide (SiO 2 ) and silicon nitride (Si 3 N 4 ) in the fourth step . 제1항 및 제3항 중 어느 하나의 항에 있어서, 상기 제4단계에서 상기 층간 절연막을 저압 기상 증착 방법으로 도포하는 것을 특징으로 하는 TFT의 제조 방법.The method of manufacturing a TFT according to any one of claims 1 to 3, wherein the interlayer insulating film is applied by a low pressure vapor deposition method in the fourth step. 제1항에 있어서, 상기 제4단계에서 소오스 영역 및 드레인 영역에 도핑된 불순물의 활성화하는 상기 층간 절연막의 전면에 레이저(Laser)의 빛을 조사하여 진행하는 것을 특징으로 하는 TFT의 제조 방법.The method of manufacturing a TFT according to claim 1, wherein in the fourth step, light is emitted from a laser on the entire surface of the interlayer insulating layer which activates the doped impurities in the source region and the drain region. 제6항에 있어서, 상기 제2절연층 전면에 조사하는 빛의 광원은 엑사이머(Excimer)레이저인 것을 특징으로 하는 TFT의 제조 방법.The method of manufacturing a TFT according to claim 6, wherein the light source of light irradiated on the entire surface of the second insulating layer is an excimer laser. 제6항에 있어서, 상기 제2절연층 전면에 조사하는 빛의 광원은 아르곤(Ar) 레이저인 것을 특징으로 하는 TFT의 제조 방법.The method of manufacturing a TFT according to claim 6, wherein a light source of light irradiated on the entire surface of the second insulating layer is an argon (Ar) laser. 제1항에 있어서, 상기 제4단계에서 소오스 영역 및 드레인 영역에 도핑된 불순물의 활성화는 저온 열처리 공정으로 진행하는 것을 특징으로 하는 TFT의 제조 방법.The method of manufacturing a TFT according to claim 1, wherein the activation of the impurities doped in the source region and the drain region in the fourth step is performed by a low temperature heat treatment process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950044897A 1995-11-29 1995-11-29 Fabrication method of thin film transistor KR100195265B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950044897A KR100195265B1 (en) 1995-11-29 1995-11-29 Fabrication method of thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950044897A KR100195265B1 (en) 1995-11-29 1995-11-29 Fabrication method of thin film transistor

Publications (2)

Publication Number Publication Date
KR970030927A true KR970030927A (en) 1997-06-26
KR100195265B1 KR100195265B1 (en) 1999-07-01

Family

ID=19436534

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950044897A KR100195265B1 (en) 1995-11-29 1995-11-29 Fabrication method of thin film transistor

Country Status (1)

Country Link
KR (1) KR100195265B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100623230B1 (en) 2003-11-29 2006-09-18 삼성에스디아이 주식회사 Method of fabricating Thin Film Transistor
KR101073727B1 (en) 2010-05-10 2011-10-13 경희대학교 산학협력단 Method for fabricating flexible top gate thin-film-transistor

Also Published As

Publication number Publication date
KR100195265B1 (en) 1999-07-01

Similar Documents

Publication Publication Date Title
KR970018635A (en) A method of forming a polycrystalline silicon layer, a thin film transistor comprising the polycrystalline silicon layer, a method of manufacturing the same, and a liquid crystal display device comprising the thin film transistor.
KR960042179A (en) Thin film transistor liquid crystal display device and manufacturing method thereof
KR970024304A (en) Thin film transistor manufacturing method
KR970030927A (en) Manufacturing Method of Thin Film Transistor
KR100188090B1 (en) Fabrication method of thin film transistor panel for lcd
KR100336771B1 (en) Transistor forming method
KR100214460B1 (en) Method for fabricating thin film transistor
KR960035905A (en) Method for manufacturing thin film transistor with drain offset structure
KR970003682A (en) MOS transistor manufacturing method with low doped drain structure
KR970054501A (en) Low doping drain thin film transistor manufacturing method
KR940012653A (en) Method of manufacturing thin film transistor
KR950021269A (en) Source / Drain Formation Method of Semiconductor Device
KR960026925A (en) Transistor manufacturing method of semiconductor device
KR970030792A (en) Manufacturing method of CMOS device
KR970030900A (en) Method of manufacturing thin film transistor
KR920011562A (en) LDD structure transistor manufacturing method
KR970054257A (en) Low doping drain thin film transistor and its manufacturing method
KR970023879A (en) Method of manufacturing thin film transistor
KR950012645A (en) Method of manufacturing thin film transistor of semiconductor device
KR970054392A (en) Transistor manufacturing method of semiconductor device
KR960026929A (en) Transistor Manufacturing Method
KR970054258A (en) Method of manufacturing thin film transistor
KR940010387A (en) Semiconductor device manufacturing method
KR960043290A (en) Thin film transistor with double gate electrode structure and manufacturing method thereof
KR960035915A (en) Method of manufacturing transistor of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20130115

Year of fee payment: 15

FPAY Annual fee payment

Payment date: 20140129

Year of fee payment: 16

FPAY Annual fee payment

Payment date: 20150130

Year of fee payment: 17

EXPY Expiration of term