KR100214460B1 - Method for fabricating thin film transistor - Google Patents
Method for fabricating thin film transistor Download PDFInfo
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- KR100214460B1 KR100214460B1 KR1019950024982A KR19950024982A KR100214460B1 KR 100214460 B1 KR100214460 B1 KR 100214460B1 KR 1019950024982 A KR1019950024982 A KR 1019950024982A KR 19950024982 A KR19950024982 A KR 19950024982A KR 100214460 B1 KR100214460 B1 KR 100214460B1
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- insulating film
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- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000010409 thin film Substances 0.000 title claims abstract description 9
- 239000010408 film Substances 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 239000011737 fluorine Substances 0.000 claims abstract description 14
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 238000005468 ion implantation Methods 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 24
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 238000010438 heat treatment Methods 0.000 claims description 4
- 230000001133 acceleration Effects 0.000 claims description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 3
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 21
- 239000001257 hydrogen Substances 0.000 abstract description 21
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 16
- 238000002161 passivation Methods 0.000 abstract description 10
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 abstract description 9
- 230000006866 deterioration Effects 0.000 abstract description 4
- -1 fluorine ions Chemical class 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 150000002431 hydrogen Chemical class 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 230000002547 anomalous effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003949 trap density measurement Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 박막트랜지스터(thin film transistor : 이하, TFT라 한다) 제조방법에 관한 것으로, 기판 상에 액티브로 사용되는 반도체층을 형성하는 공정과 ; 상기 기판과 반도체층 상에 제1 절연막을 형성하는 공정과 ; 상기 제1 절연막을 통하여 상기 반도체층에 플루오르 이온주입하는 공정과 ; 상기 제1 절연막 상에 게이트를 형성하는 공정과 ; 상기 게이트를 포함한 제1 절연막 상에 제2 절연막을 형성하는 공정과 ; 상기 제1 및 제2 절연막을 식각하여 콘택 홀을 형성하는 공정과 ; 상기 콘택 홀에 금속배선을 형성하는 공정 및 ; 상기 반도체층을 포함한 기판을 수소 처리하는 공정을 구비하여 소자제조를 완료하므로써, 1) 기존의 수소에 의한 페시베이션(passivation) 방법에서 문제시 되던 신뢰성 저하 문제를 개선할 수 있게 되며, 2) 플루오르 이온 주입으로 TFT의 이동도(mobility)를 증가시킬 수 있을 뿐 아니라 누설전류를 감소시킬 수 있게 되어 TFT 특성을 향상시킬 수 있게 된다.The present invention relates to a method for manufacturing a thin film transistor (hereinafter referred to as TFT), the method comprising: forming a semiconductor layer to be used on a substrate; Forming a first insulating film on the substrate and the semiconductor layer; Implanting fluorine ions into the semiconductor layer through the first insulating film; Forming a gate on the first insulating film; Forming a second insulating film on the first insulating film including the gate; Etching the first and second insulating films to form a contact hole; Forming a metal wiring in the contact hole; By completing the device manufacturing process by hydrogen treating the substrate including the semiconductor layer, it is possible to 1) improve the reliability deterioration problem in the existing hydrogen passivation method (passivation), 2) fluorine The ion implantation not only increases the mobility of the TFT, but also reduces the leakage current, thereby improving TFT characteristics.
Description
제1a도 및 제1b도는 종래 기술에 따른 폴리 실리콘 박막트랜지스터의 단면구조를 도시한 것으로,1a and 1b show the cross-sectional structure of a polysilicon thin film transistor according to the prior art,
제1a도는 RF 또는 ECR 수소 플라즈마를 이용한 페시베이션 방법에 의해 제조되는 박막트랜지스터 구조를 도시한 단면도.1A is a cross-sectional view showing a thin film transistor structure manufactured by a passivation method using RF or ECR hydrogen plasma.
제1b도는 실리콘 질화막을 이용한 페시베이션 방법에 의해 제조되는 박막트랜지스터 구조를 도시한 단면도.1B is a cross-sectional view showing a thin film transistor structure manufactured by a passivation method using a silicon nitride film.
제2a도 내지 제2e도는 본 발명에 따른 폴리 실리콘 박막트랜지스터 제조공정을 도시한 공정수순도.2a to 2e is a process flowchart showing a polysilicon thin film transistor manufacturing process according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 반도체기판 12 : 폴리 실리콘막10 semiconductor substrate 12 polysilicon film
12' : 액티브 폴리 실리콘막 14 : 제1 절연막12 ': active polysilicon film 14: first insulating film
16 : 플루오르 이온주입 18 : 게이트16: fluorine ion implantation 18 gate
20 : 소오스/드레인 영역 22 : 제2 절연막20 source / drain region 22 second insulating film
24 : 금속막 26 : RF 또는 ECR. 수소 플라즈마24: metal film 26: RF or ECR. Hydrogen plasma
본 발명은 액정디스플레이(liquid crystal display ; 이하, LCD라 한다)용 박막트랜지스터(thin film transistor ; 이하 TFT라 한다) 제조방법에 관한 것으로, 특히 플루오르(fluorine) 이온주입을 통하여 TFT의 특성을 개선하여 소자의 신뢰성을 향상시킨 폴리-실리콘 TFT 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a thin film transistor (hereinafter referred to as a TFT) for a liquid crystal display (hereinafter referred to as an LCD). In particular, the characteristics of the TFT are improved through fluorine ion implantation. A method for manufacturing a poly-silicon TFT with improved device reliability.
종래, LCD용 폴리-실리콘 TFT의 특성을 향상시키기 위해 일반적으로 사용되어 오던 페시베이션(passivation) 방법으로는 폴리-실리콘 TFT의 배선공정 완료후에 게이트 절연막과 액티브 폴리-실리콘 사이 또는 액티브 영역으로 사용되는 폴리-실리콘막에 수소를 확산시켜 주고, 결정입계(grain boundary)에 존재하는 트랩 수(trap state density)를 줄임으로써 폴리-실리콘 TFT의 이동도(mobility)를 증가시키고, 이와 동시에 누설전류(leakage current)를 감소시켜 TFT의 특성을 향상시켜 온 것을 들 수 있다.In the passivation method, which has been generally used to improve the characteristics of the poly-silicon TFT for LCD, it is used between the gate insulating film and the active poly-silicon or as an active region after completion of the wiring process of the poly-silicon TFT. Diffusion of hydrogen in the poly-silicon film, increasing the mobility of the poly-silicon TFT by reducing the trap state density present at the grain boundary, and at the same time leakage current current) by reducing the characteristics of the TFT.
기존에 사용되던 수소를 확산시키는 방법으로는 크게 수소 RF 플라즈마를 이용하는 방법과, ECR 수소 플라즈마에 의한 수소 확산 방법 및, RF 플라즈마에 의해 증착된 실리콘 질화막을 열처리하여 수소를 확산시키는 방법 등이 있다.As a method of diffusing hydrogen, a method of using hydrogen RF plasma, a method of hydrogen diffusion using ECR hydrogen plasma, a method of diffusing hydrogen by heat treatment of a silicon nitride film deposited by RF plasma, and the like.
제1a도 및 제1b도에는 이러한 수소 확산법을 이용하여 제조된 TFT의 단면구조가 도시되어 있으며, 여기서 제1a도는 RF 또는 ECR 수소 플라즈마를 이용한 페시베이션 방법에 의해 제조된 TFT 단면 구조를, 제1b도는 실리콘 질화막을 이용한 페시베이션 방법에 의해 제조된 TFT 단면 구조를 나타낸다. 상기 도면에서 부재번호 1은 기판을, 2는 폴리 실리콘막을, 3은 게이트 절연막을, 4는 게이트를, 5는 소오스/드레인 영역을, 6은 산화막을, 7은 금속배선을, 8은 RF 또는 ECR 수소 플라즈마 처리 공정을, 9는 보호막을 나타낸다.1A and 1B show a cross-sectional structure of a TFT manufactured using such a hydrogen diffusion method, in which FIG. 1A shows a TFT cross-sectional structure manufactured by a passivation method using RF or ECR hydrogen plasma. Figure shows a TFT cross-sectional structure manufactured by a passivation method using a silicon nitride film. In the figure, reference numeral 1 denotes a substrate, 2 denotes a polysilicon film, 3 denotes a gate insulating film, 4 denotes a gate, 5 denotes a source / drain region, 6 denotes an oxide layer, 7 denotes a metal wiring, and 8 denotes an RF or In the ECR hydrogen plasma treatment step, 9 represents a protective film.
그러나, 이와 같이 패시베이션 방법으로서 수소를 확산시켜 폴리 실리콘 TFT를 제조할 경우를 실리콘 ; 수소의 결합력(bond strength)이 약해 공정이 장시간 경과한 후, 쉽게 문턱 전압(threshold voltage)이 증가한다던지 또는 트랜스컨덕턴스(transconductance : gm)가 감소하는 등과 같은 현상이 발생하여 소자의 신뢰성이 저하되는 문제점을 가지게 된다.However, as the passivation method as described above, a case where a polysilicon TFT is manufactured by diffusing hydrogen is selected from silicon; Due to the weak bond strength of hydrogen, a phenomenon such as an increase in threshold voltage or a decrease in transconductance (gm) occurs after a long period of time, resulting in deterioration of device reliability. You have a problem.
이에 본 발명은 상기와 같은 문제점을 해결하기 위하여 이루어진 것으로, 액티브로 사용되는 반도체층이 형성된 기판전면에 절연막을 형성한 후 플루오르 이온주입을 통하여 TFT의 특성을 개선시킬 수 있도록 한 LCD용 TFT 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, a method of manufacturing a TFT for an LCD to improve the characteristics of the TFT through fluorine ion implantation after forming an insulating film on the front of the substrate on which the active semiconductor layer is formed The purpose is to provide.
상기와 같은 목적을 달성하기 위한 본 발명의 바람직한 실시예에 따른 TFT의 제조방법은 기판 상에 액티브로 사용되는 반도체층을 형성하는 공정과 ; 상기 기판과 반도체층 상에 제1 절연막을 형성하는 공정과 ; 상기 제1 절연막을 통하여 상기 반도체층에 플루오르를 이온주입하는 공정과 ; 상기 제1 절연막 상에 게이트를 형성하는 공정과 ; 상기 게이트를 포함한 제1 절연막 상에 제2 절연막을 형성하는 공정과 ; 상기 제1 및 제2 절연막을 식각하여 콘택 홀을 형성하는 공정과 ; 상기 콘택 홀에 금속배선을 형성하는 공정과, 상기 반도체층을 포함한 기판을 수소 처리하는 공정을 구비하여 형성되는 것을 특징으로 한다.Method of manufacturing a TFT according to a preferred embodiment of the present invention for achieving the above object comprises the steps of forming a semiconductor layer to be used actively on a substrate; Forming a first insulating film on the substrate and the semiconductor layer; Ion implanting fluorine into said semiconductor layer through said first insulating film; Forming a gate on the first insulating film; Forming a second insulating film on the first insulating film including the gate; Etching the first and second insulating films to form a contact hole; And forming a metal wiring in the contact hole and performing a hydrogen treatment on the substrate including the semiconductor layer.
상기 공정 결과, TFT의 신뢰성을 향상시킬 수 있게 된다.As a result of the above process, the reliability of the TFT can be improved.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
본 발명은 플루오르가 비정질 실리콘막 내에서 댕글링 본드(dangling bond)와 결합하는 성질 및 실리콘/실리콘 산화막 구조에서 실리콘 내부에 존재하는 플루오르가 후속 열처리 공정에 의해 이들의 계면이나 결함 영역으로 이동하는 성질(anomalous migration)을 이용하여 폴리 실리콘 TFT의 특성을 개선하고자 하는 것으로, 제2a도 내지 제2e도에 도시된 공정수순도를 이용하여 이를 보다 구체적으로 살펴보면 다음과 같다.The present invention relates to a property in which fluorine binds to dangling bonds in an amorphous silicon film and fluorine present in silicon in a silicon / silicon oxide film structure moves to an interface or defect region thereof by a subsequent heat treatment process. In order to improve the characteristics of the polysilicon TFT by using (anomalous migration), the process flow chart shown in FIGS. 2A through 2E is described in more detail as follows.
먼저, 제2a도에 도시된 바와 같이 기판(10)인 석영(quartz) 또는 보로실리케이트(borosilicate) 기판 상에 액티브 영역으로 사용될 폴리 실리콘을 형성하기 위하여 600℃ 이하에서 저압 또는 플라즈마 화학기상증착(LPCVD 또는 PECVD)법으로 약 1000-1500Å 두께의 비정질 실리콘막을 증착하고, 이어 600℃ 이하에서 열처리를 실시하여 비정질 실리콘을 결정화시켜 폴리 실리콘막(12)에 형성한다.First, low pressure or plasma chemical vapor deposition (LPCVD) at 600 ° C. or lower to form polysilicon to be used as an active region on a quartz or borosilicate substrate, which is a substrate 10, as shown in FIG. Alternatively, an amorphous silicon film having a thickness of about 1000-1500 kV is deposited by PECVD, and then heat-treated at 600 ° C. or lower to crystallize the amorphous silicon to form the polysilicon film 12.
그후, 제2b도에 도시된 바와 같이 사진식각법을 이용한 액티브 마스크 공정으로 폴리 실리콘막(12)을 식각하여 액티브 폴리 실리콘막(12')을 형성하고, 상기 액티브 폴리 실리콘막(12')을 포함한 기판 전면에 화학기상증착법으로 500-1000Å 두께의 제1 절연막(14)을 증착하여 이후, 플루오르 이온주입 공정시 희생(sacrificial) 산화막으로 사용하거나 또는 게이트 절연막으로 사용한다.Thereafter, as illustrated in FIG. 2B, the polysilicon film 12 is etched by an active mask process using a photolithography method to form an active polysilicon film 12 ′, and the active polysilicon film 12 ′ is formed. The first insulating film 14 having a thickness of 500-1000 Å is deposited on the entire surface of the substrate by chemical vapor deposition, and then used as a sacrificial oxide film or a gate insulating film in a fluorine ion implantation process.
이어, 상기 제1 절연막(14)을 통하여 플루오르를 이온주입한다. 이때, 가속전압은 Rp(projected range)가 실리콘/실리콘 산화막의 계면 즉, 액티브 폴리 실리콘(또는 희생성막)(12')/제1 절연막(14)의 계면에 오도록 24-40 KeV로 하고, 도우즈(dose) 주입량은 5*1014-2*1015cm-2으로 한다. 그 결과, 플루오르 첨가 효과를 극대화시킬 수 있게 된다.Subsequently, fluorine is ion implanted through the first insulating layer 14. At this time, the acceleration voltage is set to 24-40 KeV so that Rp (projected range) is at the interface of the silicon / silicon oxide film, that is, at the interface of the active polysilicon (or sacrificial film) 12 '/ first insulating film 14. Dose dose is 5 * 10 14 -2 * 10 15 cm -2 . As a result, the effect of fluorine addition can be maximized.
상기 공정 후, 다시 600℃ 이하에서 열처리를 실시하여 플루오르로 하여금 액티브 폴리 실리콘막(12') 내의 댕글링 본드와 결합하던디 또는 실리콘/실리콘 산화막 계면으로 확산시켜 계면에서의 플루오르 농도를 높여준다.After the above process, heat treatment is further performed at 600 ° C. or lower to increase fluorine concentration at the interface by diffusing fluorine with the dangling bond in the active polysilicon film 12 ′ or the silicon / silicon oxide film interface.
이로부터 액티브 폴리 실리콘막(12') 내부의 트랩 밀도(trap state densisty)를 감소시키고, 또한 계면에서의 계면(interface) 트랩 밀도를 감소시킬 수 있게 되어 폴리 실리콘 TFT의 이동도를 증가시킴과 동시에 누설전류를 줄일 수 있게 된다.From this, the trap state densisty in the active polysilicon film 12 'can be reduced, and the interface trap density at the interface can be reduced, thereby increasing the mobility of the polysilicon TFT. Leakage current can be reduced.
그 다음, 제2c도에 도시된 바와 같이 상기 제1 절연막(14) 상에 화학기상증착법으로 도프드(doped) 폴리 실리콘을 증착한 뒤 식각하여 게이트(18)를 형성하고, 이를 마스크로 소오스/드레인 영역을 정의한 후 ∼1015cm-2의 인이나 붕소를 도핑하고 열처리하여 소오스/드레인 영역(20)을 형성한다.Next, as illustrated in FIG. 2C, doped polysilicon is deposited on the first insulating layer 14 by chemical vapor deposition, and then etched to form a gate 18. After defining the drain region, the source / drain region 20 is formed by doping and heat-treating phosphorus or boron of ˜10 15 cm −2 .
계속해서, 제2d도에 도시된 바와 같이 상기 게이트(18)를 포함한 제1 절연막(14) 상에 제2 절연막(22)인 산화막을 증착화고, 소오스/드레인 영역(20)의 표면 일부가 노출되도록 제1 및 제2 절연막(14), (22)을 식각하여 콘택 홀을 형성한 뒤, 스퍼터링법으로 금속막(24)인 알루미늄-실리콘막을 형성하여 배선을 만든다.Subsequently, as illustrated in FIG. 2D, an oxide film, which is the second insulating film 22, is deposited on the first insulating film 14 including the gate 18, and a portion of the surface of the source / drain region 20 is exposed. After forming the contact holes by etching the first and second insulating films 14 and 22 as much as possible, an aluminum-silicon film, which is the metal film 24, is formed by sputtering.
이어서, 제2e도에 도시된 바와 같이 상기 패턴 상에 RF 또는 ECR 수소 플라즈마 처리(26)를 하여 수소를 액티브 영역으로 확산시킴으로써 본 공정을 완료한다.Subsequently, this process is completed by diffusing hydrogen into the active region by RF or ECR hydrogen plasma treatment 26 on the pattern as shown in FIG. 2E.
이때, 실리콘 : 플루오르의 결합력이 실리콘 : 수소의 결합력보다 약 60% 이상 크므로, 상기 공정에서와 같이 이들 두가지를 혼합하여 공정을 진행하게 되면, 기존 수소에 의한 페시베이션 방법에서 문제시 되던 소자의 신뢰성 저하 문제를 개선할 수 있게 된다.In this case, since the bonding force of silicon: fluorine is about 60% or more greater than that of silicon: hydrogen, if the two are mixed and processed as in the above process, the problem of the conventional hydrogen passivation method The problem of deterioration of reliability can be improved.
상술한 바와 같이 본 발명에 의하면, 기존의 수소에 의한 페시베이션 방법에서 문제시 되던 신뢰성 저하 문제를 개선할 수 있게 되며, 액티브로 사용되는 반도체층이 형성된 기판 전면에 절연막을 형성한후 플루오르 이온주입으로 TFT의 이동도를 증가시킬 수 있을 뿐 아니라 누설전류를 감소시킬 수 있게 되어 TFT 특성을 향상시킬 수 있게 된다.As described above, according to the present invention, it is possible to improve the reliability deterioration problem, which is a problem in the conventional hydrogen passivation method, and to form fluorine ions after forming an insulating film on the entire surface of the substrate on which the active semiconductor layer is formed. As a result, the mobility of the TFT can be increased and the leakage current can be reduced, thereby improving the TFT characteristics.
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US9093540B2 (en) | 2012-06-04 | 2015-07-28 | Samsung Display Co., Ltd. | Oxide semicondutor thin film transistor |
US9455333B2 (en) | 2012-06-04 | 2016-09-27 | Samsung Display Co., Ltd. | Thin film transistor array panel |
US9793377B2 (en) | 2012-06-04 | 2017-10-17 | Samsung Display Co., Ltd. | Thin film transistor, thin film transistor array panel including the same, and manufacturing method thereof |
USRE48290E1 (en) | 2012-06-04 | 2020-10-27 | Samsung Display Co., Ltd. | Thin film transistor array panel |
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