KR970030691A - Stacked package using lead-on chip type leadframe with a plurality of internal leads that selectively correspond to specific bonding pads of the chip - Google Patents

Stacked package using lead-on chip type leadframe with a plurality of internal leads that selectively correspond to specific bonding pads of the chip Download PDF

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Publication number
KR970030691A
KR970030691A KR1019950042101A KR19950042101A KR970030691A KR 970030691 A KR970030691 A KR 970030691A KR 1019950042101 A KR1019950042101 A KR 1019950042101A KR 19950042101 A KR19950042101 A KR 19950042101A KR 970030691 A KR970030691 A KR 970030691A
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South Korea
Prior art keywords
chip
lead
inner leads
specific bonding
leads
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KR1019950042101A
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Korean (ko)
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KR0161619B1 (en
Inventor
안민철
최기원
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김광호
삼성전자 주식회사
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Priority to KR1019950042101A priority Critical patent/KR0161619B1/en
Publication of KR970030691A publication Critical patent/KR970030691A/en
Application granted granted Critical
Publication of KR0161619B1 publication Critical patent/KR0161619B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 적층 패키지에 관한 것으로, 칩의 특정 본딩 패드에 선택적 대응되도록 형성된 복수개의 내부리드와 다른 내부리드들이 실장될 칩의 내측 부분으로 연장·형성된 리드프레임을 적용하여 적층 패키지를 구현함으로써 대형화되는 칩 크기에 대응하는 동시에 칩의 본딩 패드 설계가 용이한 특징을 갖는다.The present invention relates to a laminated package, wherein the plurality of inner leads formed to selectively correspond to a specific bonding pad of a chip and other inner leads are enlarged by implementing a laminated package by applying a lead frame extended and formed to an inner portion of the chip to be mounted. Corresponding to chip size, the bonding pad design of the chip is easy.

Description

칩의 특정 본딩 패드에 선택적 대응되는 복수개의 내부리드들을 갖는 리드 온 칩 형 리드프레임을 이용한 적층 패키지Stacked package using lead-on chip type leadframe with a plurality of internal leads that selectively correspond to specific bonding pads of the chip

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 5도는 본 발명에 의한 칩의 특정 본딩 패드에 선택적 대응되는 복수개의 내부리드들을 갖는 리드프레임을 이용한 적층 패키지를 나타내는 단면도.5 is a cross-sectional view showing a laminated package using a lead frame having a plurality of internal leads selectively corresponding to a specific bonding pad of the chip according to the present invention.

Claims (8)

복수개의 본딩 패드들을 갖는 칩과, 복수개의 내부리드들을 포함하는 리드프레임과, 상기 본딩 패드들에 각기 대응된 내부리드들을 전기적 연결하는 수단과, 상기 칩의 일 측면과 상기 내부리드들의 일 측면을 접착·지지하는 수단과, 상기 칩과 내부리드들을 포함하는 전기적 연결 부분을 봉지하는 성형 수지를 포함하는 단위 패키지가 상기 칩의 특정 본딩 패드에 선택적 대응되는 동일 목적을 갖는 내부리드들 중에서 다른 어느 하나의 내부리드에 전기적 연결되는 것을 특징으로 하는 칩의 특정 본딩 패드에 선택적 대응되는 복수개의 내부리드들을 갖는 리드 온 칩 형 리드프레임을 이용한 적층 패키지.A chip having a plurality of bonding pads, a lead frame including a plurality of inner leads, means for electrically connecting inner leads corresponding to the bonding pads, and a side of the chip and one side of the inner leads. The unit package including a means for adhering and supporting and a molding resin for encapsulating an electrical connection portion including the chip and the inner leads is any other of the inner leads having the same purpose, which selectively corresponds to a specific bonding pad of the chip. A stack package using a lead-on chip type lead frame having a plurality of inner leads selectively corresponding to specific bonding pads of a chip, wherein the lead is electrically connected to an inner lead of the chip. 제 1항에 있어서, 상기 전기적 연결하는 수단이 본딩 와이어인 것을 특징으로 하는 칩의 특정 본딩 패드에 선택적 대응되는 복수개의 내부리드들을 갖는 리드 온 칩 형 리드프레임을 이용한 적층 패키지.The stack package according to claim 1, wherein the means for electrically connecting the bonding wire is a bonding wire, the lead-on chip type lead frame having a plurality of internal leads selectively corresponding to specific bonding pads of the chip. 제 1항에 있어서, 상기 접착·지지하는 수단이 폴리이미드 계열의 접착 테이프인 것을 특징으로 하는 칩의 특정 본딩 패드에 선택적 대응되는 복수개의 내부리드들을 갖는 리드 온 칩 형 리드프레임을 이용한 적층 패키지.The laminated package using a lead-on chip type lead frame having a plurality of inner leads selectively corresponding to a specific bonding pad of the chip, wherein the means for adhering and supporting is a polyimide-based adhesive tape. 제 1항에 있어서, 상기 특정 본딩 패드에 전기적 연결되는 본딩 리드를 갖는 것을 특징으로 하는 칩의 특정 본딩 패드에 선택적 대응되는 복수개의 내부리드들을 갖는 리드 온 칩 형 리드프레임을 이용한 적층 패키지.The stack package according to claim 1, further comprising a bonding lead electrically connected to the specific bonding pad, wherein the lead-on chip type lead frame has a plurality of internal leads selectively corresponding to the specific bonding pad of the chip. 제 1항 또는 제 4항에 있어서, 상기 본딩 리드가 상기 동일 목적을 갖는 내부리드들 중의 어느 하나의 내부리드와 전기적 연결되는 것을 특징으로 하는 칩의 특정 본딩 패드에 선택적 대응되는 복수개의 내부리드들을 갖는 리드 온 칩 형 리드프레임을 이용한 적층 패키지.5. The plurality of inner leads of claim 1 or 4, wherein the bonding leads are electrically connected to any one of the inner leads having the same purpose. 6. Stacked package using lead-on chip type leadframe. 제 5항에 있어서, 상기 전기적 연결이 상기 일체로 형성되어 전기적 연결된 것을 특징으로 하는 칩의 특정 본딩 패드에 선택적 대응되는 복수개의 내부리드들을 갖는 리드 온 칩 형 리드프레임을 이용한 적층 패키지.The stack package of claim 5, wherein the electrical connection is integrally formed and electrically connected to each other, wherein the lead-on chip type leadframe has a plurality of internal leads selectively corresponding to specific bonding pads of the chip. 제 1항에 있어서, 상기 동일 목적을 갖는 내부리드들이 상기 실장된 칩의 내측으로 연장·형성된 것을 특징으로 하는 칩의 특정 본딩 패드에 선택적 대응되는 복수개의 내부리드들을 갖는 리드 온 칩 형 리드프레임을 이용한 적층 패키지.The lead-on chip lead frame having a plurality of inner leads selectively corresponding to a specific bonding pad of the chip, wherein the inner leads having the same purpose are extended and formed inside the mounted chip. Laminated package. 제 1항 또는 제 7항에 있어서, 상기 내부리드들과 상기 칩이 폴리이미드 계열의 접착제에 의해 접착·지지된 것을 특징으로 하는 칩의 특정 본딩 패드에 선택적 대응되는 복수개의 내부리드들을 갖는 리드 온 칩 형 리드프레임을 이용한 적층 패키지.8. The lead-on according to claim 1 or 7, wherein the inner leads and the chip are adhered and supported by a polyimide-based adhesive. Stacked package using chip leadframe. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950042101A 1995-11-18 1995-11-18 Stacked package using lead-on-chip type lead frame having a plurality of inner leads selectively corresponding to specified bonding pad of chip KR0161619B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950042101A KR0161619B1 (en) 1995-11-18 1995-11-18 Stacked package using lead-on-chip type lead frame having a plurality of inner leads selectively corresponding to specified bonding pad of chip

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Application Number Priority Date Filing Date Title
KR1019950042101A KR0161619B1 (en) 1995-11-18 1995-11-18 Stacked package using lead-on-chip type lead frame having a plurality of inner leads selectively corresponding to specified bonding pad of chip

Publications (2)

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KR970030691A true KR970030691A (en) 1997-06-26
KR0161619B1 KR0161619B1 (en) 1998-12-01

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