KR970029019A - Pipeline adder - Google Patents
Pipeline adder Download PDFInfo
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- KR970029019A KR970029019A KR1019950040742A KR19950040742A KR970029019A KR 970029019 A KR970029019 A KR 970029019A KR 1019950040742 A KR1019950040742 A KR 1019950040742A KR 19950040742 A KR19950040742 A KR 19950040742A KR 970029019 A KR970029019 A KR 970029019A
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- adder
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Abstract
본 발명은 파이프라인 가산기에 관한 것으로서, 2n비트데이타 A, B의 가산연산을 위해 상위 n비트와 하위 n비트로 나누어 A와 B의 상, 하위 비트들을 소정의 클럭신호에 따라서 멀티플렉싱하고, 각 하위 n비트들을 우선적으로 출력하는 2개의 2×1멀티플렉서, 하위 n비트들에 대하여 가산연산을 수행하고, 가산연산 결과 생성되는 캐리데이타를 상위 n비트들의 가산연산에 캐리로 사용하는 n비트 가산기, n비트 가산기에서 출력되는 하위 n비트들의 가산결과를 클럭신호에 따라 저장하는 파이프라인 레지스터, 파이프라인 레지스터에서 출력되는 하위 n비트 가산결과를 누적하는 하위 n비트 누적기와, n비트 가산기에서 출력되는 상위 n비트들의 가산결과를 누적하는 상위 n비트 누적기로 구성되어 하위 n비트 누적기의 출력과 상위 n비트 누적기의 출력을 연결하여 A, B의 가산연산 결과로 출력한다. 따라서, 파이프라인 개념을 도입하여 n비트 가산기로부터 2n비트 가산기를 구현함으로써 가산기의 면적을 줄이면서 고속으로 연산을 수행할 수 있도록 한다.The present invention relates to a pipeline adder, which divides the upper and lower bits of A and B into multiplexes according to a predetermined clock signal by dividing the upper n bits and the lower n bits to add 2n bit data A and B. Two 2x1 multiplexer that preferentially outputs bits, an n-bit adder that performs addition on the lower n bits, and uses a carry result generated by the addition operation as a carry on the addition of the upper n bits, n-bit A pipeline register that stores the addition result of the lower n bits output from the adder according to the clock signal, the lower n-bit accumulator accumulating the lower n-bit addition result output from the pipeline register, and the upper n bits output from the n-bit adder It consists of the upper n-bit accumulator that accumulates the addition result of the data, and connects the output of the lower n-bit accumulator and the output of the upper n-bit accumulator. W A, and outputs the result of the addition operation B. Therefore, the pipeline concept is introduced to implement a 2n-bit adder from the n-bit adder so that the operation can be performed at high speed while reducing the area of the adder.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제1도는 본 발명에 의한 파이프라인 가산기를 나타낸 블럭도,1 is a block diagram showing a pipeline adder according to the present invention;
제2a_2e도는 제1도에 있어서 각부의 동작타이밍도,2a_2e is a timing diagram of each part in FIG.
제3도는 제1도에 있어서 캐리 레지스터에 인가되는 캐리 클럭 발생방법을 설명하기 위한 회로도.3 is a circuit diagram for explaining a carry clock generation method applied to a carry register in FIG.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950040742A KR970029019A (en) | 1995-11-10 | 1995-11-10 | Pipeline adder |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950040742A KR970029019A (en) | 1995-11-10 | 1995-11-10 | Pipeline adder |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970029019A true KR970029019A (en) | 1997-06-26 |
Family
ID=66587082
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950040742A KR970029019A (en) | 1995-11-10 | 1995-11-10 | Pipeline adder |
Country Status (1)
Country | Link |
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KR (1) | KR970029019A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101974779B1 (en) * | 2018-04-16 | 2019-05-02 | 고려대학교 세종산학협력단 | Pipelined squarer for unsigned integers of up to 16 bits |
-
1995
- 1995-11-10 KR KR1019950040742A patent/KR970029019A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101974779B1 (en) * | 2018-04-16 | 2019-05-02 | 고려대학교 세종산학협력단 | Pipelined squarer for unsigned integers of up to 16 bits |
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