KR970023905A - Semiconductor L.O.C (Lead On Chip) Package Structure - Google Patents

Semiconductor L.O.C (Lead On Chip) Package Structure Download PDF

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Publication number
KR970023905A
KR970023905A KR1019950036140A KR19950036140A KR970023905A KR 970023905 A KR970023905 A KR 970023905A KR 1019950036140 A KR1019950036140 A KR 1019950036140A KR 19950036140 A KR19950036140 A KR 19950036140A KR 970023905 A KR970023905 A KR 970023905A
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KR
South Korea
Prior art keywords
chip
semiconductor
package structure
loc
package
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Application number
KR1019950036140A
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Korean (ko)
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KR100258605B1 (en
Inventor
이선구
Original Assignee
황인길
아남산업주식회사
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Application filed by 황인길, 아남산업주식회사 filed Critical 황인길
Priority to KR1019950036140A priority Critical patent/KR100258605B1/en
Publication of KR970023905A publication Critical patent/KR970023905A/en
Application granted granted Critical
Publication of KR100258605B1 publication Critical patent/KR100258605B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 반도체 L.O.C(Lead On Chip) 패키지 구조에 관한 것으로, 특히 L.O.C 패키지를 제작시 칩 상부에 설치되는 본딩패드의 위치를 자유롭게 설정할 수 있고, 또한 패키지의 두께를 얇게 제작할 수 있도록 하기 위하여 내측 중앙에 칩(11)을 구비하고 상기 칩(11) 상부 양쪽으로 칩(11)과의 부착이 용이토록 하부에 본딩패드(15)를 형성한 수개의 리드(16)를 일체로 컴파운두(17) 성형한 반도체 L.O.C패키지 구조에 있어서, 상기 본딩패드(15)를 이방성 전도필름(12)으로 형성하여 상부에 회로설계에 입각한 수개의 범프(13)를 일체로 형성한 칩(11)에 열압착을 이용하여 상호 회로적으로 연결형성 되도록 구성함을 특징으로 하는 반도체 L.O.C 패키지 구조.The present invention relates to a structure of a semiconductor lead on chip (LOC) package, and in particular, in order to be able to freely set a position of a bonding pad installed on an upper portion of a chip when manufacturing a LOC package, and to make a thin package thickness. Compound 17 is integrally provided with several leads 16 having a chip 11 at both ends and bonding pads 15 formed at the bottom of the chip 11 so as to be easily attached to both sides of the chip 11. In the molded semiconductor LOC package structure, the bonding pad 15 is formed of an anisotropic conductive film 12 and thermo-compression bonded to a chip 11 having integrally formed several bumps 13 based on a circuit design. The semiconductor LOC package structure, characterized in that configured to be connected to each other by using a circuit.

Description

반도체 L.O.C(Lead On Chip) 패키지 구조Semiconductor L.O.C (Lead On Chip) Package Structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 의한 L.O.C 패키지 구조를 나타내는 것으로,Figure 2 shows the L.O.C package structure according to the present invention,

(가)는 본딩 패드가 중심부에 부착된 상태를 나타낸 정단면도이고,(A) is a front sectional view showing a state where the bonding pad is attached to the center part,

(나)는 본딩 패드가 외곽에 부착된 상태를 나타내는 정단면도,(B) is a front sectional view showing a state in which a bonding pad is attached to the outside;

제3도는 본 발명에 의한 본딩 패드의 구조를 나타내는 것으로,3 shows the structure of a bonding pad according to the present invention,

(가)는 칩 상부에 접착전의 상태를 나타낸 요부 단면도이고,(A) is a sectional view of the principal parts showing the state before bonding to the upper part of the chip,

(나)는 칩 상부에 접착 후의 상태를 나타내는 요부 단면도.(B) is sectional drawing of the principal part which shows the state after bonding to the upper part of a chip | tip.

Claims (4)

내측 중앙에 칩(11)을 구비하고 상기 칩(11) 상부 양쪽으로 칩(11)과의 부착이 용이토록 하부에 본딩 패드(15)를 형성한 수개의 리드(16)를 일체로 컴파운드(17) 성형한 반도체 L.O.C패키지 구조에 있어서, 상기 본딩패드(15)를 이방성 전도필름(12)으로 형성하여 상부에 회로설계에 입각한 수개의 범프(13)를 일체로 형성한 칩(11)에 열압착을 이용하여 상호 회로적으로 연결형성 되도록 구성함을 특징으로 하는 반도체 L.O.C 패키지 구조.The compound 17 is integrally formed with several leads 16 having a chip 11 at an inner center and a bonding pad 15 formed at a lower side of the chip 11 so as to be easily attached to both sides of the chip 11. In the molded semiconductor LOC package structure, the bonding pads 15 are formed of an anisotropic conductive film 12, and a plurality of bumps 13 based on a circuit design are integrally formed on the chip 11. A semiconductor LOC package structure, which is configured to be connected to each other by crimping. 제1항에 있어서, 이방성 전도필름(12)으로 형성된 본딩패드(15)를 일체로 형성하여 리드(16)와 칩(11)을 상호 회로적으로 연결 구성함을 특징으로 하는 반도체 L.O.C 패키지 구조.The semiconductor L.O.C package structure according to claim 1, wherein the bonding pads (15) formed of the anisotropic conductive film (12) are integrally formed to interconnect the leads (16) and the chips (11). 제1항 또는 제2항에 있어서, 칩(11) 상부로 돌출형성된 범프(13)의 높이를 이방성 전도필름(12)으로 형성된 본딩 패드(15) 두께의 약 80% 이하로 형성함을 특징으로 하는 반도체 L.O.C 패키지 구조.The method of claim 1 or claim 2, characterized in that the height of the bump 13 protruding above the chip 11 is formed to about 80% or less of the thickness of the bonding pad 15 formed of the anisotropic conductive film 12. Semiconductor LOC package structure. 제1항에 있어서, 패키지(10)의 몰드(17)된 부위의 내측으로 위치하게 되는 리드(16)를 외측으로 하향경사지게 절곡형성함을 특징으로 하는 반도체 L.O.C 패키지 구조.The semiconductor L.O.C package structure according to claim 1, wherein the lead (16) which is located inward of the mold (17) of the package (10) is bent downwardly to the outside. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950036140A 1995-10-19 1995-10-19 Structure of semiconductor l.o.c package KR100258605B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950036140A KR100258605B1 (en) 1995-10-19 1995-10-19 Structure of semiconductor l.o.c package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950036140A KR100258605B1 (en) 1995-10-19 1995-10-19 Structure of semiconductor l.o.c package

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KR970023905A true KR970023905A (en) 1997-05-30
KR100258605B1 KR100258605B1 (en) 2000-06-15

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