KR970023853A - Manufacturing method of insulating layer between polysilicon layers - Google Patents
Manufacturing method of insulating layer between polysilicon layers Download PDFInfo
- Publication number
- KR970023853A KR970023853A KR1019950036151A KR19950036151A KR970023853A KR 970023853 A KR970023853 A KR 970023853A KR 1019950036151 A KR1019950036151 A KR 1019950036151A KR 19950036151 A KR19950036151 A KR 19950036151A KR 970023853 A KR970023853 A KR 970023853A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- layer
- organosilane
- polysilicon
- ozone
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명의 목적은, 반도체장치의 구조에 중간층 유전체를 발생시키는 방법을 제공함에 있다. 본 발명의 방법은, DRAM구조내에서 의 중간층 유전체를 형성가공하기 위하여 비교적 균일하고도 용이한 방법을 제공한다.An object of the present invention is to provide a method for generating an interlayer dielectric in the structure of a semiconductor device. The method of the present invention provides a relatively uniform and easy method for forming and processing an interlayer dielectric in a DRAM structure.
실질적으로 균일한 중간층 유전체층을 가지는 집적회로의 형성가공법은, 제1폴리실리콘을 가지는 국부적으로 완성된 반도체 웨이퍼(400)를 제공하는 스텝과, 약 1기압의 압력으로 국부적으로 완성된 반도체 장치의 폴리 실리콘층 및 그 부분을 피복하는 유전체층(405)을 침적하는 스텝과, 유전체층의 부분을 피복하여 제2폴리실리콘층을 형성하는 스텝을 구비하는 것으로, 해당 유전체층의 침적스텝은, 200g/m2및 이하의 농도로, 유기실런 및 오존을 결합하여 실행된다.An integrated circuit forming and processing method having a substantially uniform intermediate layer dielectric layer comprises the steps of providing a locally completed semiconductor wafer 400 having a first polysilicon and a poly of a semiconductor device locally completed at a pressure of about 1 atmosphere. And depositing the silicon layer and the dielectric layer 405 covering the portion thereof, and forming the second polysilicon layer by covering the portion of the dielectric layer, wherein the deposition step of the dielectric layer is 200 g / m 2 ; It is performed by combining organosilane and ozone at the following concentrations.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제4도는, 본 발명에 의한 간략한 형성가공법을 나타낸다.4 shows a simplified forming process according to the present invention.
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950036151A KR100220225B1 (en) | 1995-10-19 | 1995-10-19 | Process for forming interlayer insulator between polysilicon layers |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950036151A KR100220225B1 (en) | 1995-10-19 | 1995-10-19 | Process for forming interlayer insulator between polysilicon layers |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970023853A true KR970023853A (en) | 1997-05-30 |
KR100220225B1 KR100220225B1 (en) | 1999-09-15 |
Family
ID=19430668
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950036151A KR100220225B1 (en) | 1995-10-19 | 1995-10-19 | Process for forming interlayer insulator between polysilicon layers |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100220225B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100855276B1 (en) | 2007-07-27 | 2008-09-01 | 주식회사 하이닉스반도체 | Method for manufacturing of low dielectrics |
-
1995
- 1995-10-19 KR KR1019950036151A patent/KR100220225B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100220225B1 (en) | 1999-09-15 |
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