KR100271400B1 - Isolating manufacturing method for semiconductor device using tranch structure - Google Patents

Isolating manufacturing method for semiconductor device using tranch structure Download PDF

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KR100271400B1
KR100271400B1 KR1019980013232A KR19980013232A KR100271400B1 KR 100271400 B1 KR100271400 B1 KR 100271400B1 KR 1019980013232 A KR1019980013232 A KR 1019980013232A KR 19980013232 A KR19980013232 A KR 19980013232A KR 100271400 B1 KR100271400 B1 KR 100271400B1
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trench
high density
insulating film
forming
density plasma
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KR1019980013232A
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Korean (ko)
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KR19990080169A (en
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김서원
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황인길
아남반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02249—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by combined oxidation and nitridation performed simultaneously
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE: A method for manufacturing an insulating layer of a semiconductor device using a trench structure is provided to control a current leakage, by forming an oxide nitride layer on the surface of a trench because of chemical reaction of a nitrogen doping layer and an oxide layer doped in the trench. CONSTITUTION: A pad oxide layer(12) and a nitride layer(13) are sequentially formed on a semiconductor substrate(11). The nitride layer, the pad oxide layer and the substrate are sequentially etched to form a trench by an etch process using a photoresist layer pattern for isolation. Nitrogen ions are doped to the outer wall of the trench by a high density plasma process. An insulating layer is deposited to fill the trench by a high density plasma chemical vapor deposition method.

Description

트랜치 구조를 이용한 반도체 소자의 절연막 형성방법Method of forming insulating film of semiconductor device using trench structure

본 발명은 반도체 소자의 제조방법에 관한 것으로써, 더욱 상세하게는 산화 나이트 라이드(oxinitride)층에 의해 누설전류를 방지하는 소자분리 영역이 형성된 모스 전계효과 트랜지스터를 제조하기 위한 트랜치 구조를 이용한 반도체 소자의 절연막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor device using a trench structure for manufacturing a MOS field effect transistor having a device isolation region for preventing leakage current by an oxidizing layer. It relates to a method for forming an insulating film of.

일반적으로 반도체 소자의 고집적화 추세에 따라 반도체 소자의 제조공정에서 반도체 기판면에 형성된 각 소자를 전기적으로 분리해야한다. 바이폴러 트랜지스터 디바이스에서는 물론이지만, 반도체 소자 디바이스에서도 인접한 소자 사이에서 바람직하지 않은 관계가 생기지 않도록 필드 산화막을 두껍게 하거나, 채널형성 방지용 확산을 하는 것으로 아이솔레이션(isollation) 기술에 의한 소자분리 영역을 형성한다.In general, in accordance with the trend toward higher integration of semiconductor devices, each device formed on the surface of a semiconductor substrate must be electrically separated in the manufacturing process of the semiconductor device. As well as in bipolar transistor devices, semiconductor device devices also form device isolation regions by isolation techniques by thickening the field oxide film or by diffusing to prevent channel formation so as to avoid undesirable relationships between adjacent devices.

반도체 소자에서 소자분리 영역을 형성하는 아이솔레이션 기술에서는 LOCOS(local oxidation of silicon)구조와 얕은 트랜치 소자분리(shallow trench isolation : STI)구조가 있으나 STI구조가 소자를 전기적으로 확실히 분리하여 전기적으로 완전히 플로팅이 되기 때문에 더 많이 응용되고 있다.Isolation technology, which forms device isolation regions in semiconductor devices, includes local oxidation of silicon (LOCOS) structures and shallow trench isolation (STI) structures. More applications.

이하, 도1a - 도1d를 참조하여 종래의 트랜치 구조를 이용한 반도체 소자의 절연막 형성방법을 설명하면 다음과 같다.Hereinafter, an insulating film forming method of a semiconductor device using a conventional trench structure will be described with reference to FIGS. 1A to 1D.

도1a에 도시되어 있는바와 같이, 반도체 기판(1)상부 전면에 걸쳐 열산화 공정으로 패드 산화막(2)을 형성한 다음, 반도체 기판(1) 상부 전면에 걸쳐 화학 기상 증착법(chemical vapor deposition : CVD)으로 질화막(3)을 증착하여 형성한다.As shown in FIG. 1A, a pad oxide film 2 is formed by a thermal oxidation process over the entire upper surface of the semiconductor substrate 1, and then chemical vapor deposition (CVD) is performed over the entire upper surface of the semiconductor substrate 1. The nitride film 3 is formed by evaporation.

이 후, 연속해서 상기 질화막(3) 상부 전면에 감광막을 도포하여 리소그래피 공정에 의해 트랜치를 형성하기 위한 감광막 패턴을 형성한 후, 질화막(3)과 패드 산화막(2)을 식각공정에 의해 식각하여 반도체 기판(1)의 표면을 노출시킨다.Thereafter, a photoresist film is applied to the entire upper surface of the nitride film 3 to form a photoresist pattern for forming a trench by a lithography process, and then the nitride film 3 and the pad oxide film 2 are etched by an etching process. The surface of the semiconductor substrate 1 is exposed.

이 후, 표면이 노출된 반도체 기판(1)을 식각 공정에 의해 건식 식각하여 해자 트랜치(moat trench)구조(4)의 소자분리 영역을 형성한다.Thereafter, the semiconductor substrate 1 having the exposed surface is dry-etched by an etching process to form an isolation region of the moat trench structure 4.

다음, 도1b에 도시되어 있는바와 같이, 열산화 공정에 의해 트랜치(4) 내에 라이너 산화막(liner oxide)(5)을 형성한다. 이 때, 라이너 산화막(5)은 고온의 열산화 공정으로 장시간동안 수행하여 수백(Å)의 두께의 치밀한 산화막을 형성한다.Next, as shown in FIG. 1B, a liner oxide 5 is formed in the trench 4 by a thermal oxidation process. At this time, the liner oxide film 5 is performed for a long time by a high temperature thermal oxidation process to form a dense oxide film having a thickness of several hundreds.

또한, 트랜치(4) 내에 라이너 산화막(5)을 형성함에 있어서, 트랜치(4) 끝부분으로 전류가 누설됨을 방지하기 위해 2회에 걸친 열산화 공정으로 트랜치(4)의 끝부분을 코너 라운딩(conner rounding)(9)으로 형성한다.Further, in forming the liner oxide film 5 in the trench 4, the corners of the trench 4 may be corner-rounded by two thermal oxidation processes to prevent leakage of current to the ends of the trench 4. conner rounding) (9).

다음, 도1c에 도시되어 있는바와 같이, 반도체 기판(1)전면에 걸쳐 CVD공정으로 산화막(6)을 증착하여 트랜치(4)을 메우고, 상기 산화막(6)을 소자분리 영역의 절연막으로 형성한다.Next, as shown in FIG. 1C, an oxide film 6 is deposited over the entire surface of the semiconductor substrate 1 by a CVD process to fill the trench 4, and the oxide film 6 is formed as an insulating film of an element isolation region. .

다음, 도1d에 도시되어 있는바와 같이, 소자분리 영역의 절연막으로 증착된 산화막(6)을 어닐링 공정에 의해 열처리하여 고밀도 절연막(7)으로 형성한다.Next, as shown in FIG. 1D, the oxide film 6 deposited as the insulating film in the element isolation region is heat-treated by an annealing process to form a high density insulating film 7.

이와 같이 종래의 방법으로 트랜치 구조를 이용한 반도체 소자의 절연막을 형성방법은 트랜치 끝부분으로 전류의 누설을 방지하기 위해 코너 라운딩으로 형성해야하는등 제조 공정이 복잡하고, 또한 코너 라운딩등 소자분리 영역 형성 조건이 부적합 할 경우, 여러 가지 형태로 소자분리 영역에서 누설 전류가 발생하여 래치-업 및 소자분리 특성이 저하되는 문제점이 있다.As described above, the method of forming an insulating film of a semiconductor device using a trench structure in the conventional method is complicated in the manufacturing process such as forming a corner rounding to prevent leakage of current at the end of the trench, and also requires a condition for forming an isolation region such as corner rounding. If this is not suitable, there is a problem in that leakage current occurs in the device isolation region in various forms, thereby degrading the latch-up and device isolation characteristics.

따라서 본 발명은 상기한 문제점을 해결하기 위해 안출된 것으로써, 그 목적은 반도체 소자의 제조 공정 단순화하고, 동시에 반도체 소자의 래치-업 및 소자분리 특성을 향상시킬 수 있는 트랜치 구조를 이용한 반도체 소자의 절연막 형성방법을 제공하기 위한 것이다.Accordingly, the present invention has been made to solve the above problems, the object of which is to simplify the manufacturing process of the semiconductor device, and at the same time to improve the latch-up and device isolation characteristics of the semiconductor device using a trench structure It is to provide a method for forming an insulating film.

도1a - 도1d는 종래의 트랜치 구조를 이용한 반도체 소자의 절연막 형성 공정 순서를 개략적으로 도시한 단면도이고,1A to 1D are cross-sectional views schematically showing a process of forming an insulating film of a semiconductor device using a conventional trench structure,

도2a - 도2c는 본 발명의 실시예에 따른 트랜치 구조를 이용한 반도체 소자의 절연막 형성 공정순서를 개략적으로 도시한 단면도이다.2A to 2C are cross-sectional views schematically illustrating a process of forming an insulating film of a semiconductor device using a trench structure according to an embodiment of the present invention.

상기한 목적을 달성하기 위한 본 발명은,The present invention for achieving the above object,

소자분리를 위해 반도체 기판 전면에 형성된 질화막과 패드 산화막을 감광막 패턴에 따라 식각하여 반도체 기판의 표면을 노출시킨 다음, 노출된 반도체 기판 표면을 식각공정으로 트랜치를 형성한 다음, 절연막을 증착하여 소자분리 영역을 형성하는 반도체 소자에 있어서, 상기 트랜치에 고밀도 프라즈마 공정으로 질소를 도핑하는 단계와;For the device isolation, the nitride film and the pad oxide film formed on the front surface of the semiconductor substrate are etched according to the photoresist pattern to expose the surface of the semiconductor substrate, and then the trench is formed on the exposed surface of the semiconductor substrate by an etching process. A semiconductor device forming a region, comprising: doping nitrogen into a trench in a high density plasma process;

상기 절연막은 산화막을 고밀도 프라즈마 화학 기상 증착법을 이용 반도체 기판 전면에 증착하여 트랜치를 메운 다음, 어닐링 공정으로 열처리하여 고밀도 절연막으로 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The insulating film is formed by depositing an oxide film on the entire surface of the semiconductor substrate by using a high density plasma chemical vapor deposition method, and then heat-treating by an annealing process to form a high density insulating film.

상기한 목적을 구체적으로 달성하여 실현할 수 있는 본 발명의 실시예를 첨부한 도면을 참조로 상세히 설명한다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention, which can be achieved and realized in detail by the above objects, will be described in detail with reference to the accompanying drawings.

도2a - 도2c는 본 발명의 실시예에 따른 트랜치 구조를 이용한 반도체 소자의 절연막 형성방법 공정 순서를 개략적으로 도시한 단면도로서, 도2a에 도시되어 있는바와 같이 반도체 기판(11)의 상부 표면에 열산화 공정으로 패드 산화막(12)을 성장시켜 형성한 다음, 상기 반도체 기판(11) 상부 전면에 걸쳐 CVD공정으로 질화막(13)을 증착시켜 형성한다.2A to 2C are cross-sectional views schematically illustrating a process sequence for forming an insulating film of a semiconductor device using a trench structure according to an embodiment of the present invention, and are shown on the upper surface of the semiconductor substrate 11 as shown in FIG. After the pad oxide film 12 is grown by thermal oxidation, the nitride film 13 is deposited by CVD over the entire upper surface of the semiconductor substrate 11.

이어서, 감광막을 질화막(13) 상부 표면에 도포한 다음, 리소그래프 공정으로 감광막 패턴을 형성한 후, 식각하여 질화막(13)과 패드 산화막(12)을 제거한 다음 반도체 기판(11)의 표면을 노출시킨다.Subsequently, a photoresist film is applied to the upper surface of the nitride film 13, and then a photoresist pattern is formed by a lithography process, followed by etching to remove the nitride film 13 and the pad oxide film 12, and then to expose the surface of the semiconductor substrate 11. Let's do it.

다음, 노출된 반도체 기판(11)의 표면을 식각공정으로 건식 식각하여 트랜치(14)를 형성한다.Next, the trench 14 is formed by dry etching the exposed surface of the semiconductor substrate 11 by an etching process.

이 후, 도2b에 도시되어 있는바와 같이, 트랜치(14) 구조로 형성된 반도체 기판(11)을 선택적 고밀도 프라즈마 도핑공정으로 불순물 예를 들어 바람직하게는 질소(N) 이온을 트랜치(14) 외벽에 도핑시켜 질소 도핑층(15)을 형성한다.Thereafter, as shown in FIG. 2B, the semiconductor substrate 11 having the trench 14 structure is subjected to a selective high density plasma doping process, and impurities, for example, preferably nitrogen (N) ions, are formed on the outer wall of the trench 14. Doping to form a nitrogen doped layer 15.

상기 질소 도핑층(15)을 형성하기 위한 고밀도 프라즈마는 1E8 ions/cm3이상으로 프라즈마의 소스는 제한을 하지 않는다.The high density plasma for forming the nitrogen doped layer 15 is 1E8 ions / cm 3 or more, and the source of the plasma is not limited.

이어서, 고밀도 프라즈마 화학 기상 증착법(PECVD : plasma enhanced chemical vapor deposition)으로 반도체 기판(11) 전면에 걸쳐 산화막(16)을 증착하여 소자분리 영역을 형성한다.Subsequently, an oxide layer 16 is deposited over the entire surface of the semiconductor substrate 11 by high density plasma enhanced chemical vapor deposition (PECVD) to form an isolation region.

상기 소자분리 영역은 고밀도 프라즈마 도핑공정으로 트랜치(14) 외벽에 질소 도핑층(15)을 형성한 동일 장비내에서 대기와의 접촉없이 연속해서 고밀도 PECVD 공정으로 반도체 기판(11) 전면에 산화막(15)을 증착하여 트랜치(14)을 메워 형성한다.The device isolation region is formed on the entire surface of the semiconductor substrate 11 by a high density PECVD process continuously without contact with the air in the same equipment in which the nitrogen doping layer 15 is formed on the outer wall of the trench 14 by a high density plasma doping process. ) To form the trench 14 by filling it.

이 때, 상기 질소 도핑층(15)과 산화막(16)이 증착된 트랜치(14) 외벽 계면사이에는 도2c에 도시되어 있는바와 같이, 도핑된 질소(15)와 증착된 산화막(16)이 화학 반응하여 수십(Å) 이하의 두께로 산화 나이트 라이드(17)층을 자연적으로 형성한다.At this time, between the nitrogen doped layer 15 and the outer wall interface of the trench 14 on which the oxide film 16 is deposited, as shown in FIG. 2C, the doped nitrogen 15 and the deposited oxide film 16 are chemically deposited. By reacting, a layer of nitride oxide 17 is naturally formed to a thickness of several tens or less.

이와 같이 형성된 산화 나이트 라이드(17)층은 열산화 공정과 상압 화학 기상 증착법(APCVD : atomspheric pressure chemical vapor deposition)에 의해 형성되는 산화막에 비해 밀도 및 절연특성이 매우 우수하여 소자분리 영역 형성에 따른 누설 전류의 발생을 억제한다.The nitride oxide layer 17 formed as described above has excellent density and insulation characteristics compared to the oxide film formed by the thermal oxidation process and the atmospheric pressure chemical vapor deposition (APCVD). Suppresses the generation of current.

다음, 상기에서 소자분리 영역의 절연막으로 증착된 산화막(16)을 어닐링 공정으로 열처리하여 고밀도 절연막(18)으로 형성한다.Next, the oxide film 16 deposited as the insulating film in the device isolation region is heat-treated by an annealing process to form a high density insulating film 18.

이 때, 열처리는 기존의 퍼니스(furnace) 공정 또는 RTA공정을 이용하여 수행한다.At this time, the heat treatment is carried out using a conventional furnace (furnace) process or RTA process.

상기한 실시예는 가장 바람직한 실시예를 설명한 것으로써, 이에 한정되는 것은 아니며, 상기 실시예로부터 용이하게 설명할 수 있는 것도 본 발명에 포함된다.The above embodiments are described as the most preferred embodiments, and the present invention is not limited thereto, and the embodiments can be easily described from the above embodiments.

이상에서와 같이 본 발명의 실시예서 고밀도 프라즈마 공정으로 트랜치에 도핑된 질소 도핑층과 절연막으로 증착되는 산화막이 화학 반응으로 트랜치 표면에 산화 나이트 라이드층이 자연히 형성되어 전류의 누설을 억제시킴에 따라, 래치-업 및 소자분리 특성을 향상시키고, 반도체 소자의 제조 공정을 단순화시킨다.As described above, according to the embodiment of the present invention, as the nitrogen doped layer doped in the trench and the oxide film deposited by the insulating layer are chemically reacted, the nitride layer is naturally formed on the trench surface to suppress leakage of current. It improves latch-up and device isolation characteristics and simplifies the manufacturing process of semiconductor devices.

Claims (7)

반도체 기판 상부에 패드 산화막과 질화막을 형성하는 단계와;Forming a pad oxide film and a nitride film over the semiconductor substrate; 소자분리를 위한 감광막 패턴을 이용한 식각 공정으로 상기 질화막과 패드 산화막, 기판을 순차적으로 식각하여 트랜치를 형성하는 단계와;Forming a trench by sequentially etching the nitride film, the pad oxide film, and the substrate by an etching process using a photoresist pattern for device isolation; 고밀도 플라즈마 공정으로 상기 트랜치 외벽에 질소를 도핑하는 단계와;Doping nitrogen into the trench outer wall in a high density plasma process; 고밀도 플라즈마 화학 기상 증착법으로 절연막을 증착하여 상기 트랜치를 매입하는 단계를 포함하는 것을 특징으로 하는 트랜치 구조를 이용한 반도체 소자의 절연막 형성방법.And depositing the trench by depositing an insulating film by a high density plasma chemical vapor deposition method. 청구항 1에 있어서, 고밀도 프라즈마 공정으로 상기 트랜치 외벽에 질소를 도핑하는 단계에서,The method of claim 1, wherein in the step of doping nitrogen to the trench outer wall in a high density plasma process, 상기 고밀도 프라즈마는 1E8 ions/cm3이상인 것을 특징으로 하는 트랜치 구조를 이용한 반도체 소자의 절연막 형성방법.The high density plasma is a method of forming an insulating film of a semiconductor device using a trench structure, characterized in that 1E8 ions / cm 3 or more. 청구항 1에 있어서, 고밀도 플라즈마 공정으로 상기 트랜치 외벽에 질소를 도핑하는 단계와 고밀도 플라즈마 화학 기상 증착법으로 절연막을 증착하여 상기 트랜치를 매입하는 단계는,The method of claim 1, wherein the doping of the trench with an outer wall of the trench in a high density plasma process and depositing an insulating film by using a high density plasma chemical vapor deposition method to embed the trench, 동일한 장비내에서 대기와의 접촉없이 연속적으로 실시하는 것을 특징으로 하는 트랜치 구조를 이용한 반도체 소자의 절연막 형성방법.A method of forming an insulating film of a semiconductor device using a trench structure, characterized in that the same structure is carried out continuously without contact with the atmosphere. 청구항 1에 있어서, 상기 절연막을 고밀도 절연막으로 형성하기 위한 열처리 공정을 더 포함하는 것을 특징으로 하는 트랜치 구조를 이용한 반도체 소자의 절연막 형성방법.The method of forming an insulating film of a semiconductor device using a trench structure according to claim 1, further comprising a heat treatment process for forming the insulating film into a high density insulating film. 청구항 1에 있어서, 트랜치 외벽에 도핑된 질소와 증착된 산화막이 화학 반응하여 상기 트랜치 외벽 계면사이에 산화 나이트 라이드층이 형성되는 것을 특징으로 하는 트랜치 구조를 이용한 반도체 소자의 절연막 형성방법.The method of claim 1, wherein a nitride oxide layer is formed between the trench outer wall interface by chemical reaction between the doped nitrogen and the deposited oxide film on the trench outer wall. 청구항 5에 있어서, 상기 산화 나이트 라이드층은 90(Å) 이하의 두께로 형성되는 것을 특징으로 트랜치 구조를 이용한 반도체 소자의 절연막 형성방법.The method of claim 5, wherein the nitride oxide layer is formed to a thickness of 90 μm or less. 청구항 4에 있어서, 상기 열처리는 퍼니스(furnace) 공정 또는 RTA공정을 이용하여 수행하는 것을 특징으로 하는 트랜치 구조를 이용한 반도체 소자의 절연막 형성방법.The method of claim 4, wherein the heat treatment is performed using a furnace process or an RTA process.
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