KR970013690A - Glitch-independent control signal generator - Google Patents
Glitch-independent control signal generator Download PDFInfo
- Publication number
- KR970013690A KR970013690A KR1019950024830A KR19950024830A KR970013690A KR 970013690 A KR970013690 A KR 970013690A KR 1019950024830 A KR1019950024830 A KR 1019950024830A KR 19950024830 A KR19950024830 A KR 19950024830A KR 970013690 A KR970013690 A KR 970013690A
- Authority
- KR
- South Korea
- Prior art keywords
- pulse
- outputs
- clock signal
- control signal
- circuit
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
본 발명은 신호 지연에 의해 발생하는 글리치(glitch)에 영향을 받지 않는 제어신호 발생회로에 관한 것이다. 카운터수단(100)은 제1클럭신호CK1을 수신하여 상기의 제1클럭신호CK1에 동기되어 정해진 일련의 상태들을 수행하여 출력a0~a5들을 출력한다. 디코더수단(210)은 카운터수단(100)의 출력a0~a5를 디코드하여 출력X1, X2를 출력하며 출력X1, X2는 카운터수단(100)의 출력들a0~a5가 제1클럭신호보다 지연되어 출력되므로 글리치가 발생한다. 글리치필터수단(220)은 디코더수단(210)은 출력들X1, X2를 수신하여 제2클럭신호CK2에 동기되어 디코더수단(210)의 출력에서 발생하는 글리치를 제거하여 긴 폭의 펄스를 출력하기 위하여 긴 폭의 펄스의 시작은 나타내는 제1펄스 및 긴 폭의 펄스의 끝을 나타내는 제2펄스를 출력한다. 래치수단(300)은 제1펄수가 하이논리값을 가질때부터 제2펄스가 하이논리값을 가질때까지 하이논리값을 갖는 긴 폭의 펄스를 출력한다.The present invention relates to a control signal generating circuit which is not affected by the glitch generated by the signal delay. The counter means 100 receives the first clock signal CK1, performs a series of states determined in synchronization with the first clock signal CK1, and outputs outputs a0 to a5. The decoder means 210 decodes the outputs a0 to a5 of the counter means 100 and outputs outputs X1 and X2. The outputs X1 and X2 are delayed by the outputs a0 to a5 of the counter means 100 than the first clock signal. The output produces glitches. The glitch filter means 220, the decoder means 210 receives the outputs X1, X2 and outputs a long pulse by removing the glitch generated at the output of the decoder means 210 in synchronization with the second clock signal CK2. For this reason, the start of the long pulse outputs a first pulse representing the long pulse and the second pulse representing the end of the long pulse. The latch means 300 outputs a long pulse having a high logic value from when the first pulse has a high logic value to when the second pulse has a high logic value.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950024830A KR0154798B1 (en) | 1995-08-11 | 1995-08-11 | Control signal generating circuit depend on the glitch |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950024830A KR0154798B1 (en) | 1995-08-11 | 1995-08-11 | Control signal generating circuit depend on the glitch |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970013690A true KR970013690A (en) | 1997-03-29 |
KR0154798B1 KR0154798B1 (en) | 1998-12-15 |
Family
ID=19423344
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950024830A KR0154798B1 (en) | 1995-08-11 | 1995-08-11 | Control signal generating circuit depend on the glitch |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0154798B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100400735B1 (en) * | 1999-12-30 | 2003-10-08 | 엘지전자 주식회사 | Method and Circuit for detecting glitch signal |
KR101422919B1 (en) * | 2012-09-05 | 2014-07-23 | 삼성전기주식회사 | Motor driving apparatus, and operating method thereof |
-
1995
- 1995-08-11 KR KR1019950024830A patent/KR0154798B1/en not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100400735B1 (en) * | 1999-12-30 | 2003-10-08 | 엘지전자 주식회사 | Method and Circuit for detecting glitch signal |
KR101422919B1 (en) * | 2012-09-05 | 2014-07-23 | 삼성전기주식회사 | Motor driving apparatus, and operating method thereof |
Also Published As
Publication number | Publication date |
---|---|
KR0154798B1 (en) | 1998-12-15 |
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