KR960038549A - Data Synchronous Clock Generator - Google Patents

Data Synchronous Clock Generator Download PDF

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Publication number
KR960038549A
KR960038549A KR1019950008203A KR19950008203A KR960038549A KR 960038549 A KR960038549 A KR 960038549A KR 1019950008203 A KR1019950008203 A KR 1019950008203A KR 19950008203 A KR19950008203 A KR 19950008203A KR 960038549 A KR960038549 A KR 960038549A
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KR
South Korea
Prior art keywords
data
output
clock
processing means
synchronization
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Application number
KR1019950008203A
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Korean (ko)
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KR0146060B1 (en
Inventor
김영일
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문정환
엘지반도체 주식회사
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Application filed by 문정환, 엘지반도체 주식회사 filed Critical 문정환
Priority to KR1019950008203A priority Critical patent/KR0146060B1/en
Publication of KR960038549A publication Critical patent/KR960038549A/en
Application granted granted Critical
Publication of KR0146060B1 publication Critical patent/KR0146060B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

본 발명은 데이타 동기발생 장치에 관한 것으로, 종래에는 데이타동기를위한 클럭을 발진에 의해 생성함으로 임의의 상황에서 클럭의 시작 시점이 변화되는 경우 출력 데이타가 로우가 되는 시작 시점이 랜덤하게 되어 데이타의 손실을 초래하는 문제점이 있었다. 이러한 점을 개선하기 위하여 본 발명은 데이타의 변화를 검출하여 변화가 발생할 때마다 펄스를 발생시키고 그 펄스에 동기되어 데이타의 변화값을 출력하도록 구성한 것으로, 본 발명은 데이타의 변화를 검출 시점을 결정함으로 클럭의 시작 시점이 다르더라도 안정된 데이타 출력을 얻을 수 있어 데이타 손실을 방지할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data synchronization generating device. In the related art, a clock for data synchronization is generated by oscillation so that when a start point of a clock changes in an arbitrary situation, a start point at which output data goes low becomes random. There was a problem causing loss. In order to improve this point, the present invention is configured to detect a change in data, generate a pulse whenever a change occurs, and output a change value of the data in synchronization with the pulse. This ensures stable data output even at different clock start points, thus preventing data loss.

Description

데이타 동기 클럭 발생장치Data Synchronous Clock Generator

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 데이타 동기 클럭 발생 장치의 블럭도, 제4도는 제3도에서 각 부의 파형도, 제5도는 제3도에서 제1, 제2 신호 처리부의 회로도.3 is a block diagram of the data synchronization clock generator of the present invention, FIG. 4 is a waveform diagram of each part in FIG. 3, and FIG. 5 is a circuit diagram of the first and second signal processing sections in FIG.

Claims (4)

클럭(CLK)의 레벨이 변화할때마다 펄스(CLK-P)를 발생시키는 제1신호 처리 수단과, 입력 데이타(DATA-IN)의 레빌이 변화할때마다 펄스(DATA-P)를 발생시키는 제2신호 처리수단과, 상기 제1처리 수단의 출력 펄스( DATA-P)에 동기되어 상기 입력 데이타(DATA-IN)를 래치함에 의해 데이타(DATA-L)를 출력하는 제1래치 수단과, 상기 제2신호 처리 수단의 출력(DATA-P)에 동기되어 상기 제1래치 수단의 출력 데이터 (DATA-L)를 래치함에 의해 데이터의 변화값(DATA-OUT)를 출력하는 제2래치 수단으로 구성한 것을 특징으로 하는 데이타 동기 클럭 발생 장치.First signal processing means for generating a pulse CLK-P whenever the level of the clock CLK changes, and generating a pulse DATA-P whenever the level of the input data DATA-IN changes. A second latch processing means, a first latch means for outputting data DATA-L by latching the input data DATA-IN in synchronization with an output pulse DATA-P of the first processing means; Second latch means for outputting the change value DATA-OUT of the data by latching the output data DATA-L of the first latch means in synchronization with the output DATA-P of the second signal processing means. A data synchronous clock generator, comprising: 제1항에 있어서, 제1, 제2신호 처리 수단은 입력 신호(IN)를 반전하는 반전기와, 상기 입력 신호(IN)를 소정 기간 지연하는 지연기와, 이 지연기를 출력 신호와 상기 반전기의 출력 신호를 배타적 노아링하여 펄스를 발생시키는 배타적 노아게이트로 각기 구성한 것을 특징으로 하는 데이타 동기 클럭 발생 장치.2. The apparatus of claim 1, wherein the first and second signal processing means comprise: an inverter for inverting the input signal IN, a delayer for delaying the input signal IN for a predetermined period, and the delayer for the output signal and the inverter. A data synchronization clock generator comprising: an exclusive noar gate for generating pulses by exclusively outputting signals. 제1항에 있어서, 제1래치 수단은 제1신호 처리 수단의 출력(CLK-P)을 클럭으로 하여 입력 단자(D)의 데이타(DATA-IN)를 래치함에 의해 반전 단자(Q)로 데이타(DATA-P)를 출력하는 플립플롭인 것을 특징으로 하는 데이타 동기 클럭 방생 장치.2. The first latch means according to claim 1, wherein the first latch means latches the data DATA-IN of the input terminal D with the output CLK-P of the first signal processing means as a clock, thereby providing data to the inverting terminal Q. A data synchronous clock generation device characterized by being a flip-flop which outputs (DATA-P). 제1항에 있어서, 제2래치 수단은 제2신호 처리수단의 출력(DATA-P)을 클럭으로 하여 제1래치 수단의 출력(DATA-L)을 래치함에 의해 비반전 단자(Q)로 데이타의 변화값(DATA-OUT)을 출력하는 플립플롭인 것을 특징으로 하는 데이타 동기 클럭 장치.2. The second latch means according to claim 1, wherein the second latch means latches the output DATA-L of the first latch means with the output DATA-P of the second signal processing means as a clock, thereby data is transmitted to the non-inverting terminal Q. And a flip-flop for outputting a change value (DATA-OUT) of the data synchronization clock device.
KR1019950008203A 1995-04-08 1995-04-08 Clock generator KR0146060B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950008203A KR0146060B1 (en) 1995-04-08 1995-04-08 Clock generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950008203A KR0146060B1 (en) 1995-04-08 1995-04-08 Clock generator

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Publication Number Publication Date
KR960038549A true KR960038549A (en) 1996-11-21
KR0146060B1 KR0146060B1 (en) 1998-09-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100433648B1 (en) * 1995-05-02 2004-08-12 텔레폰아크티에볼라게트 엘엠 에릭슨 Delay-matched clock and data signal generator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100433648B1 (en) * 1995-05-02 2004-08-12 텔레폰아크티에볼라게트 엘엠 에릭슨 Delay-matched clock and data signal generator

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KR0146060B1 (en) 1998-09-15

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