KR970007822B1 - Fabricating method of semiconductor device - Google Patents
Fabricating method of semiconductor device Download PDFInfo
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- KR970007822B1 KR970007822B1 KR1019930024234A KR930024234A KR970007822B1 KR 970007822 B1 KR970007822 B1 KR 970007822B1 KR 1019930024234 A KR1019930024234 A KR 1019930024234A KR 930024234 A KR930024234 A KR 930024234A KR 970007822 B1 KR970007822 B1 KR 970007822B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 14
- 230000000903 blocking effect Effects 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 17
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 8
- 229910052804 chromium Inorganic materials 0.000 description 5
- 239000011651 chromium Substances 0.000 description 5
- 239000010453 quartz Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000011159 matrix material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000001579 optical reflectometry Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/50—Mask blanks not covered by G03F1/20 - G03F1/34; Preparation thereof
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
제1도는 종래 콘택홀 상에 형성되는 감광막패턴의 일실시예의 평면도.1 is a plan view of an embodiment of a photosensitive film pattern formed on a conventional contact hole.
제2도는 (A) 및 (B)는 감광막 패턴을 형성하되, 제1도에서의 선 Ⅱ-Ⅱ의 단면에 따라 도시한 제조공정도.FIG. 2 is a manufacturing process diagram which shows (A) and (B) the photosensitive film pattern, and is taken along the cross section of the line II-II in FIG.
제3도는 종래 콘택홀 상에 형성되는 감광막패턴의 다른 실시예의 평면도.3 is a plan view of another embodiment of a photosensitive film pattern formed on a conventional contact hole.
제4도는 본 발명에 따른 감광막 패턴 형성을 위한 노광 마스크의 일실시예의 평면도.4 is a plan view of one embodiment of an exposure mask for forming a photosensitive film pattern according to the present invention.
제5도는 제4도에서의 선Ⅴ-Ⅴ에 따른 단면도.FIG. 5 is a cross-sectional view taken along the line VV of FIG. 4.
제6도는 제4도의 노광 마스크를 사용한 반도체 장치의 단면도.6 is a cross-sectional view of a semiconductor device using the exposure mask of FIG.
제7도는 본 발명에 따른 감광막 패턴 형성을 위한 노광 마스크의 다른 실시예의 평면도.7 is a plan view of another embodiment of an exposure mask for forming a photosensitive film pattern according to the present invention.
제8도는 제7도에서의 선Ⅷ-Ⅷ에 따른 단면도.FIG. 8 is a cross-sectional view taken along line VII-VII in FIG. 7.
제9도는 제7도의 노광 마스크를 사용한 반도체 장치의 단면도.9 is a cross-sectional view of a semiconductor device using the exposure mask of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11,21 : 반도체 기판12,22 : 감광막11,21 semiconductor substrate 12,22 photosensitive film
13,23 : 콘택 홀15,25 : 하부층13,23 contact hole 15,25 lower layer
16,26 : 중간층17,27 : 상부층16,26 middle layer 17,27 upper layer
18,28 : 석영기판19,29,39 : 크롬 패턴18,28: quartz substrate 19,29,39: chrome pattern
20,30,40 : 노광 마스크31 : 도트 패턴20,30,40 Exposure mask 31 Dot pattern
41 : 보조 패턴41: auxiliary pattern
본 발명은 반도체 장치의 제조 방법에 관한 것으로서, 특히 반도체 장치의 상하 배선을 연결시키는 콘택홀 형성시 장치 표면의 심한 굴곡이나, 난반사에 의해 감광막이 손상되는 나칭 현상을 방지하여 미세한 콘택홀을 정확하게 형성하여 신뢰성을 향상시킬 수 있는 반도체 장치의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, when contact holes for connecting upper and lower wirings of a semiconductor device are formed, the microscopic contact holes are precisely formed by preventing a severe bending of the surface of the device or a chipping phenomenon in which the photoresist film is damaged by diffuse reflection. The present invention relates to a semiconductor device manufacturing method capable of improving reliability.
최근 반도체 장치의 고집적화 추세는 미세 패턴 형성기술의 발전에 큰 영향을 받고 있으며, 특히 감광막 패턴은 반도체 장치의 제조 공정중에서 식각 또는 이온 주입 공정등의 마스크로 매우 폭 넓게 사용되고 있다. 따라서 감광막 패턴의 미세화, 공정 진행의 안정성, 공정 완료 후의 깨끗한 제거 그리고 잘못 형성된 감광막 패턴을 제거하고 다시 형성하는 재작업의 용이성 등이 필요하게 되어 많은 연구가 진행되고 있다.In recent years, the trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology. In particular, the photoresist pattern is widely used as a mask for etching or ion implantation in the semiconductor device manufacturing process. Therefore, there is a need for miniaturization of photoresist patterns, stability of process progression, clean removal after completion of processes, and ease of rework to remove and re-form incorrectly formed photoresist patterns.
반도체 장치의 고집적화에 따라 상하의 도전선을 연결하는 콘택과 주변 배선과의 간격이 감소되어 콘택홀의 크기는 감소되고, 콘택홀의 지름과 깊이의 비인 에스팩트 비(aspect ratio)는 감소한다. 따라서, 다층의 도전선을 구비하는 반도체 장치에서 콘택을 형성하기 위하여 제조 공정의 정확하고 엄격한 정렬이 요구된다. 또한 콘택 크기의 감소는 반도체 제조 장비의 고정밀성을 요구하게 되며, 어느 정도 이하 크기의 미세패턴, 예를들어 0.4㎛이하의 패턴 형성이 현재의 장비로는 매우 어려운 문제점이 있다.As the semiconductor device is highly integrated, the distance between the contact connecting the upper and lower conductive lines and the peripheral wiring is reduced, so that the size of the contact hole is reduced, and the aspect ratio, which is the ratio of the diameter and depth of the contact hole, is reduced. Thus, accurate and stringent alignment of the manufacturing process is required to form contacts in semiconductor devices having multiple conductive wires. In addition, the reduction of the contact size requires high precision of the semiconductor manufacturing equipment, there is a problem that it is very difficult to form a micropattern of a certain size or less, for example, 0.4㎛ or less with current equipment.
이러한 콘택 홀의 간격 유지를 위하여 콘택 설계시 상부 도전선 식각 마스크와 콘택 홀 식각 마스크는 일정한 설계규칙에 따르며, 이때 다음과같은 요소들을 고려하여야 한다.In order to maintain the distance between the contact holes, the upper conductive line etch mask and the contact hole etch mask follow a certain design rule when designing a contact, and the following factors should be considered.
첫째, 패턴 형성시의 오배열 여유(misalignment tolerance), 렌즈 왜곡(lens distortion), 임계크기 변화(critical dimention variation).First, misalignment tolerance, lens distortion, and critical dimention variation in pattern formation.
둘째, 마스크간의 정합(registration).Second, registration between masks.
세째, 콘택 홀 내의 절연막 두께등과 같은 요인들을 고려하여야 한다.Third, factors such as the thickness of the insulating film in the contact hole should be considered.
일반적인 감광막 패턴 형성 공정은 감광제 및 수지(resin)등이 용제인 솔밴트에 일정 비율로 용해되어 있는 감광액을 도포한 후, 선택적으로 광을 조사하고, 현상하여 감광막 패턴을 형성한다.In a general photosensitive film pattern forming step, a photosensitive solution dissolved in a fixed ratio in a solvent, in which a photosensitive agent, a resin, and the like is applied, is selectively irradiated with light and developed to form a photosensitive film pattern.
상기와 같은 습식 공정(wet process)에 의한 미세 패턴화의 한계를 극복하기 위하여 다층 감광막 방법이나, 위상 반전 마스크를 사용하거나 실리레이션(silylation)방법등이 연구되고 있다.In order to overcome the limitation of the micro patterning by the wet process as described above, a multilayer photoresist method, a phase inversion mask, or a sillation method has been studied.
종래 반도체 장치는 라인간의 간격은 감소되고 라인 자체의 폭도 감소되어 몇차례의 공정을 거치게 되면 표면의 굴곡이 심해지다. 따라서 제1도에 도시되어 있는 바와같이 굴곡이 심한 반도체 기판(11)상에 감광막(12) 패턴을 형성할 경우, 콘택홀(13)부군의 감광막(12) 패턴이 손상되는 나칭 현상이 일어나게 되며, 심할 경우 패턴이 단선되는등의 문제점이 있다.In the conventional semiconductor device, the spacing between the lines is reduced and the width of the lines itself is also reduced, and the surface of the semiconductor device undergoes several processes. Therefore, when the photosensitive film 12 pattern is formed on the highly curved semiconductor substrate 11 as shown in FIG. 1, a naming phenomenon occurs in which the photosensitive film 12 pattern of the contact hole 13 subgroup is damaged. If severe, the pattern is broken.
이러한 제조과정을 제2도 (A) 및 (B)를 참조하여 살펴보면 다음과 같다. 먼저, 반도체 기판(11)상에 순차적으로 형성되어 있는 하부층(15)및 중간층(16)의 소정 부분이 순차적으로 제거되어 콘택홀(13)이 형성되어 있으며, 상기 구조의 전표면에 상부층(17)이 도포되어 있다. 상기 상부층(17)상에 패턴을 형성하고자 하는 감광막(12)을 도포한다. 이때 상기 감광막(12)은 비노광영역이 패턴이 되는 포지티브형 감광액으로 형성된다.Looking at this manufacturing process with reference to Figure 2 (A) and (B) as follows. First, a predetermined portion of the lower layer 15 and the intermediate layer 16 sequentially formed on the semiconductor substrate 11 is sequentially removed to form a contact hole 13. The upper layer 17 is formed on the entire surface of the structure. ) Is applied. The photosensitive film 12 to form a pattern is coated on the upper layer 17. In this case, the photosensitive film 12 is formed of a positive photosensitive liquid in which a non-exposed area is a pattern.
그다음, 상기 콘택홀(13)을노출시키는 크롬 패턴(18)이 석영기판(19)상에 형성되어 있는 노광 마스크(20)를 사용하여 상기 감광막(12)을 노광한다. 이때 상기 상부층(17)이 광반사율이 높은 물질, 예를들어 알루미늄 일때, 상기 상부층(17)의 경사면에서 난반사된 빛에 의해 상기 감광막(12)의 패턴으로 예정된 부분의 에지 상측이 노광된다.(제2도(A)참조).Next, the photosensitive film 12 is exposed using the exposure mask 20 formed on the quartz substrate 19 with the chrome pattern 18 exposing the contact hole 13. At this time, when the upper layer 17 is made of a material having high light reflectivity, for example, aluminum, the upper side of the edge of the predetermined portion in the pattern of the photosensitive film 12 is exposed by light diffusely reflected from the inclined surface of the upper layer 17. See Figure 2 (A).
그후, 상기 감광막(12)을 현상하여 상기 콘택홀(13) 상부를 노출시키는 감광막(12) 패턴을 형성한다. 이때 난반사된 광에 노광된 상기 감광막(12)패턴의 에지 상측이 함께 제거되어 전체적인 패턴의 형상이 불완전하게 된다.(제2도 (B)참조).Thereafter, the photoresist 12 is developed to form a photoresist 12 pattern exposing the upper portion of the contact hole 13. At this time, the upper edge of the pattern of the photosensitive film 12 exposed to the diffusely reflected light is removed together, resulting in an incomplete shape of the overall pattern (see FIG. 2B).
상기와 같이 콘택홀 및 배선등과 같은 기판의 경사면에서 반사된 광에 의해 감광막의 비노광 영역으로 예정된 부분이 노광되며, 이러한 현상은 반사면이 광반사율이 높은 금속 물질일 경우 더욱 심하게 일어난다.As described above, the predetermined portion is exposed to the non-exposed area of the photosensitive film by the light reflected from the inclined surface of the substrate such as contact hole and wiring, and this phenomenon occurs more severely when the reflective surface is a metal material having high light reflectance.
또한 다른 실시예로서, 제3도에 도시되어 있는 바와 같이 반도체 기판(11)상에 형성되어 있는 감광막(12)패턴이 콘택홀(13)과 중첩되어 있는 경우에도 감광막(12)의 에지 부분이 손상된다.As another embodiment, as shown in FIG. 3, the edge portion of the photosensitive film 12 may be formed even when the photosensitive film 12 pattern formed on the semiconductor substrate 11 overlaps with the contact hole 13. Damaged.
상술한 바와같이 종래 반도체 장치에서 하부층들의 기복에 의해 경사면에서 반사되는 광이 감광막의 비노광 영역으로 예정된 부분을 노광시켜 감광막 패턴의 에지 상측이 제거되어 손상되는 나칭(notching)형상이 발생되는 문제점이 있다. 특히 상기 경사면이 광반사율이 높은 물질이면 이러한 문제점이 더욱 증가되어 패턴이 단락되기도 한다.As described above, in the conventional semiconductor device, the light reflected from the inclined surface due to the undulation of the lower layers exposes a predetermined portion to the non-exposed area of the photoresist layer, thereby causing a notching shape in which the upper edge of the photoresist pattern is removed and damaged. have. In particular, if the inclined surface is a material having a high light reflectance, this problem is further increased and the pattern may be shorted.
이러한 문제점을 해결하기 위하여 비.피.에스.지(boro phopho silicate glass; BPSG)등과 같은 유동성이 강한 물질을 도포하여 기판의 기복을 평탄화 하거나, 금속층상에 광반사율이 낮은 물질(anti reflection coating)을 도포한 후 감광막 패턴을 형성하거나, 감광막상에 저반사 물질을 도포한 후 패턴잉하는 등의 방법에 의해 난반사 현상을 줄이고 있다.In order to solve this problem, a highly fluid material such as boro phopho silicate glass (BPSG) is applied to flatten the undulation of the substrate, or a material having low light reflectance on the metal layer. After the coating, the diffuse reflection phenomenon is reduced by a method of forming a photosensitive film pattern or applying a low reflective material onto the photosensitive film and then patterning the same.
그러나 이러한 방법들을 통상의 감광막 패턴 형성 공정에 비해 별도의 공정들이 추가되어 반도체 장치의 생산성을 떨어뜨리고, 제조 단가를 상승되며, 공정이 복잡해지는 등의 문제점이 있다.However, these methods have a problem in that separate processes are added as compared to the general photosensitive film pattern forming process, thereby decreasing the productivity of the semiconductor device, increasing the manufacturing cost, and complicating the process.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 별도의 매트릭스형 광차단막 패턴들이 형성되어 있는 노광 마스크를 사용하여 경사면에서의 광반사를 감소시켜, 별도의 추가 공정없이 감광막 패턴의 나칭 현상을 방지하여 공정을 간편하게 하며, 생산성을 향상시킬 수 있는 반도체 장치의 제조방법을 제공함에 있다.The present invention is to solve the above problems, an object of the present invention is to reduce the light reflection on the inclined surface by using an exposure mask in which the separate matrix light blocking film patterns are formed, a photosensitive film pattern without additional processing It is to provide a method of manufacturing a semiconductor device that can simplify the process by preventing the naching phenomenon of the, and improve the productivity.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 장치 제조방법의 특징은, 경사면을 갖는 기판의 상측에 감광막 패턴을 형성하는 반도체 장치의 제조방법에 있어서, 상기 기판의 경사면에 대응되는 부분에 소정 크기로된 매트릭스 형상의 도트 패턴을 구비하는 노광 마스크로 감광막을 노광하여 경사면에서 반사되는 광의 세기를 감소시켜 광반사에 의한 감광막 패턴의 손상을 방지함에 있다.A feature of the semiconductor device manufacturing method according to the present invention for achieving the above object is a method of manufacturing a semiconductor device for forming a photosensitive film pattern on the upper side of the substrate having an inclined surface, a predetermined portion corresponding to the inclined surface of the substrate An exposure mask having a matrix pattern of sized dot patterns is used to expose the photoresist to reduce the intensity of light reflected from the inclined surface, thereby preventing damage to the photoresist pattern due to light reflection.
또한 본발명에 따른 반도체 장치 제조 방법의 다른 특징은, 경사면을 갖는 기판의 상측에 감광막 패턴을 형성하는 반도체 장치의 제조방법에 있어서, 상기 기판의 경사면에서 반사되는 광에 노출되는 부분에 노광되는 광을 차단하는 광차단막 패턴을 구비하는 노광 마스크로 노광하여 광반사에 의한 감광막 패턴의 손상을 방지함에 있다.Further, another feature of the semiconductor device manufacturing method according to the present invention is a method of manufacturing a semiconductor device in which a photosensitive film pattern is formed on a substrate having an inclined surface, wherein the light is exposed to a portion exposed to the light reflected from the inclined surface of the substrate. It is to prevent the damage of the photosensitive film pattern by light reflection by exposing with an exposure mask having a light blocking film pattern for blocking the light.
이하, 본 발명에 따른 반도체 장치의 제조 방법에 관하여 첨부도면을 참조하여 상세히 설명한다.EMBODIMENT OF THE INVENTION Hereinafter, the manufacturing method of the semiconductor device which concerns on this invention is demonstrated in detail with reference to attached drawing.
제4도 및 제5도는 본 발명에 따른 반도체 장치의 제조공정에 사용되는 노광 마스크의 일실시예를 설명하기 위한 도면들로서, 서로, 연관시켜 설명한다.4 and 5 are views for explaining an embodiment of an exposure mask used in the manufacturing process of a semiconductor device according to the present invention, and will be described in association with each other.
상기의 노광 마스크(31)는 포지티브 감광막용으로서, 석영기판(28)상에 패턴으로 예정된 부분의 광을 차단하는 크롬으로된 광차단막 패턴(29)이 일려로 형성되어 있다. 또한 상기 광차단막 패턴(29)들 사이의 중앙부분에 광반사 제어용으로 정사각 형상의 도트 패턴(31)들이 형성되어 있으며, 상기 도트 패턴(31)들은 크롬등과 같은 광차단 물질이거나, 석영, 에스.오.지(spin on glass;SOG)등과 같은 위상반전 물질로 형성되어 있다. 상기 도트 패턴(31)들이 광차단 물질로 형성될 경우 도트 패턴(31)자체에 의한 상을 감광막에 남기지 않을 정도의 작은 크기, 예를들어 0.1~0.3㎛정도의 크기로 형성하여 반사되는 빛의 량을 감소시킨다. 상기 도트 패턴(31)을 위상반전 물질로 형성할 경우에는 위상이 반전된 광과 그렇지 않은 광과의 간섭에 의해 경사면에서의 광반사를 방지한다. 또한 상기 도트 패턴(31)은 빛을 어느정도, 예를들어 50% 이하로 투과시키는 하프 톤형 패턴일 수도 있다.The above-mentioned exposure mask 31 is for a positive photoresist film, and a light blocking film pattern 29 made of chromium for blocking light of a portion predetermined as a pattern on a quartz substrate 28 is formed in one piece. In addition, square dot patterns 31 are formed in a central portion between the light blocking layer patterns 29 for light reflection control, and the dot patterns 31 are light blocking materials such as chromium, quartz, S It is formed of a phase inversion material such as spin on glass (SOG). When the dot patterns 31 are formed of a light blocking material, the size of the light reflected by forming a small size such that the dot pattern 31 itself does not leave an image on the photoresist film, for example, about 0.1 to 0.3 μm Reduce the amount. When the dot pattern 31 is formed of a phase inversion material, light reflection on an inclined surface is prevented by interference between light having a phase inverted and light that is not. In addition, the dot pattern 31 may be a half-tone pattern that transmits light to a certain degree, for example, 50% or less.
따라서 도트 패턴(31)을 구비하는 노광 마스크(30)를 사용하여 노광 공정을 진행하면, 제6도에 도시되어 있는 바와같은 정확한 감광막 패턴(22)이 형성된다. 즉 반도체 기판(21)상에 하부층(25), 중간층(26)이 소정부분 제거되어 콘택홀(23)이 형성되어 있다. 또한 상기 중간층(26)상에 상기 콘택홀(23)을 메우는 상부층(27)이 도포되어 있으며, 상기 상부층(27)상에 에지부분이 손상되지 않는 감광막(23)패턴이 형성된다.Therefore, when the exposure process is performed using the exposure mask 30 having the dot pattern 31, the accurate photosensitive film pattern 22 as shown in FIG. 6 is formed. That is, the lower layer 25 and the intermediate layer 26 are removed from the predetermined portion on the semiconductor substrate 21 to form the contact hole 23. In addition, an upper layer 27 filling the contact hole 23 is coated on the intermediate layer 26, and a photosensitive layer 23 pattern is formed on the upper layer 27 so that edge portions thereof are not damaged.
또한 콘택홀의 일측이 감광막 패턴과 증첩되는 경우에는 제7도 및 제8도에 도시되어 있는 노광 마스크(40)를 사용한다. 상기 노광 마스크(40)는 석영 기판(38)상에 노광 영역을 정의하는 크롬 패턴(39)들이 소정 간격으로 형성되어 있으며, 상기 크롬 패턴(39)의 일측에 콘택홀과 중첩되는 부분에 보조패턴(41)이 형성되어 있다. 상기 보조 패턴(41)은 크롬등과 같은 광차단 물질이나, 에스.오.지 등과 같은 위상 반전 물질로, 경사면의 광 반사에 의해 손상이 예정되는 부분 즉 콘택홀(23)부분을 완전히 덮도록 형성되며, 상기 코롬패턴(39)들은 보조 패턴(41)에 의해 단락되지 않을 정도로 충분한 간격을 유지한다.In addition, when one side of the contact hole is folded with the photosensitive film pattern, the exposure mask 40 shown in FIGS. 7 and 8 is used. The exposure mask 40 has chromium patterns 39 defining exposure regions on the quartz substrate 38 at predetermined intervals, and an auxiliary pattern is formed at a portion of the chromium pattern 39 overlapping the contact hole. (41) is formed. The auxiliary pattern 41 is a light blocking material such as chromium or a phase inversion material such as S.O.G, and the like, so as to completely cover a portion to be damaged due to light reflection of an inclined surface, that is, a portion of the contact hole 23. The color patterns 39 are spaced apart from each other so as not to be shorted by the auxiliary pattern 41.
따라서, 반도체 기판(21)상에 콘택홀(23)을 구비하는 상부층(27), 중간층(26)및 하부층(25)이 순차적으로 형성되어 있으며, 상기 보조 패턴(41)에 의해 상기 상부층(27)상에 상기 콘택홀(23)쪽으로 돌출된 감광막 패턴(22)이 형성되어 나칭 현상을 방지한다.Accordingly, the upper layer 27, the intermediate layer 26, and the lower layer 25 having the contact holes 23 are sequentially formed on the semiconductor substrate 21, and the upper layer 27 is formed by the auxiliary pattern 41. ) Is formed on the photoresist pattern 22 protruding toward the contact hole 23 to prevent the naching phenomenon.
이상에서 설명한 바와같이, 본 발명에 따른 반도체 장치의 제조방법은 경사면을 갖는 반도체 기판의 노광 공정시 경사면에 해당되는 부분에 도트 패턴을 구비하는 노광 마스크를 사용하거나, 경사면에 해당되는 부분으로의 노광을 방지하기 위한 보조 패턴이 크롬 패턴들의 사이에 형성한 노광 마스크를 사용하여 경사면에서의 반사광에 의해 감광막의 예정되지 않은 부분이 노광되어 감광막이 손상되는 것을 방지하였으므로, 종래의 삼층 레지스트 법이나, 저반사물질을 이용하는 방법에 비해 공정이 간단하여 공정 수율을 증가시키고, 신뢰성을 향상시킬 수 있는 효과가 있다.As described above, the method of manufacturing a semiconductor device according to the present invention uses an exposure mask having a dot pattern in a portion corresponding to the inclined surface during the exposure process of the semiconductor substrate having the inclined surface, or exposes the portion to the inclined surface. By using the exposure mask formed between the chrome patterns, the auxiliary pattern for preventing the damage of the photosensitive film is prevented from being exposed by the reflected light on the inclined surface, thereby preventing damage to the photosensitive film. Compared with the method using the reflective material, the process is simple, so that the process yield can be increased and reliability can be improved.
Claims (4)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930024234A KR970007822B1 (en) | 1993-11-15 | 1993-11-15 | Fabricating method of semiconductor device |
| JP28064494A JPH07219206A (en) | 1993-11-15 | 1994-11-15 | Photomask |
| US08/339,826 US5508133A (en) | 1993-11-15 | 1994-11-15 | Photo mask |
| CN94118243A CN1118456A (en) | 1993-11-15 | 1994-11-15 | Photo mask |
| DE4440821A DE4440821C2 (en) | 1993-11-15 | 1994-11-15 | Photomask to avoid irregular light reflections |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930024234A KR970007822B1 (en) | 1993-11-15 | 1993-11-15 | Fabricating method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950015591A KR950015591A (en) | 1995-06-17 |
| KR970007822B1 true KR970007822B1 (en) | 1997-05-17 |
Family
ID=19368080
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930024234A KR970007822B1 (en) | 1993-11-15 | 1993-11-15 | Fabricating method of semiconductor device |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5508133A (en) |
| JP (1) | JPH07219206A (en) |
| KR (1) | KR970007822B1 (en) |
| CN (1) | CN1118456A (en) |
| DE (1) | DE4440821C2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08314113A (en) * | 1995-05-17 | 1996-11-29 | Fujitsu Ltd | Mask and printed circuit board formed by using the same |
| US5866913A (en) * | 1995-12-19 | 1999-02-02 | International Business Machines Corporation | Proximity correction dose modulation for E-beam projection lithography |
| US6228279B1 (en) * | 1998-09-17 | 2001-05-08 | International Business Machines Corporation | High-density plasma, organic anti-reflective coating etch system compatible with sensitive photoresist materials |
| KR100476366B1 (en) * | 2002-04-17 | 2005-03-16 | 엘지.필립스 엘시디 주식회사 | Thin film transistor array substrate and method of manufacturing the same |
| US6835504B2 (en) * | 2002-05-13 | 2004-12-28 | Macronix International Co., Ltd. | Photomask with illumination control over patterns having varying structural densities |
| US6811933B2 (en) * | 2002-07-01 | 2004-11-02 | Marc David Levenson | Vortex phase shift mask for optical lithography |
| CN100442475C (en) * | 2003-12-30 | 2008-12-10 | 中芯国际集成电路制造(上海)有限公司 | Method and structure for manufacturing halftone mask for semiconductor wafer |
| JP6795323B2 (en) | 2016-04-07 | 2020-12-02 | 日東電工株式会社 | Wiring circuit board and its manufacturing method |
| JP6787693B2 (en) | 2016-06-07 | 2020-11-18 | 日東電工株式会社 | Wiring circuit board manufacturing method |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0611672B2 (en) * | 1985-02-08 | 1994-02-16 | 秀之 川村 | Man-made mineral fiber molding |
| JPS6220844U (en) * | 1985-07-22 | 1987-02-07 | ||
| JPS62135837A (en) * | 1985-12-10 | 1987-06-18 | Matsushita Electric Ind Co Ltd | Photomask and photoengraving method using same |
| JPS62276552A (en) * | 1986-05-26 | 1987-12-01 | Hitachi Micro Comput Eng Ltd | Pattern forming mask and method for fabricating electronic device by using it |
| US4902899A (en) * | 1987-06-01 | 1990-02-20 | International Business Machines Corporation | Lithographic process having improved image quality |
| JPH02151862A (en) * | 1988-12-05 | 1990-06-11 | Omron Tateisi Electron Co | Mask for photolithography and production thereof |
| JPH03142466A (en) * | 1989-10-30 | 1991-06-18 | Hitachi Ltd | Production of semiconductor device and mask used for the production |
| JPH03186845A (en) * | 1989-12-15 | 1991-08-14 | Mitsubishi Electric Corp | Photomask for semiconductor integrated circuit |
| JPH04268556A (en) * | 1991-02-25 | 1992-09-24 | Oki Electric Ind Co Ltd | Formation of resist pattern |
| JP2771907B2 (en) * | 1991-05-24 | 1998-07-02 | 三菱電機株式会社 | Photomask and method of manufacturing the same |
| JPH05142748A (en) * | 1991-11-25 | 1993-06-11 | Mitsubishi Electric Corp | Phase shift mask and its production |
| US5411824A (en) * | 1993-01-21 | 1995-05-02 | Sematech, Inc. | Phase shifting mask structure with absorbing/attenuating sidewalls for improved imaging |
-
1993
- 1993-11-15 KR KR1019930024234A patent/KR970007822B1/en not_active IP Right Cessation
-
1994
- 1994-11-15 US US08/339,826 patent/US5508133A/en not_active Expired - Lifetime
- 1994-11-15 DE DE4440821A patent/DE4440821C2/en not_active Expired - Fee Related
- 1994-11-15 CN CN94118243A patent/CN1118456A/en active Pending
- 1994-11-15 JP JP28064494A patent/JPH07219206A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| DE4440821A1 (en) | 1995-05-18 |
| JPH07219206A (en) | 1995-08-18 |
| US5508133A (en) | 1996-04-16 |
| CN1118456A (en) | 1996-03-13 |
| KR950015591A (en) | 1995-06-17 |
| DE4440821C2 (en) | 1997-05-28 |
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