KR960039369A - Capacitor Manufacturing Method of Semiconductor Memory Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Memory Device Download PDF

Info

Publication number
KR960039369A
KR960039369A KR1019950008715A KR19950008715A KR960039369A KR 960039369 A KR960039369 A KR 960039369A KR 1019950008715 A KR1019950008715 A KR 1019950008715A KR 19950008715 A KR19950008715 A KR 19950008715A KR 960039369 A KR960039369 A KR 960039369A
Authority
KR
South Korea
Prior art keywords
conductive layer
forming
material layer
layer pattern
pattern
Prior art date
Application number
KR1019950008715A
Other languages
Korean (ko)
Other versions
KR0165382B1 (en
Inventor
김태욱
김태룡
박진호
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950008715A priority Critical patent/KR0165382B1/en
Publication of KR960039369A publication Critical patent/KR960039369A/en
Application granted granted Critical
Publication of KR0165382B1 publication Critical patent/KR0165382B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

반도체 메모리장치의 커패시터 제조방법에 대하여 개시한다. 이는 반도체기판 상에 제1도전층을 형성하는 제1공정, 제1도전층 상에 제1물질층을 형성하는 제2공정, 스토리지전극이 형성될 영역의 제1물질층을 제거함으로써 제1물질층 패턴을 형성하는 제3공정, 제1물질층 패턴의 측벽에 제2도전층 패턴을 형성하는 제4공정, 제1물질층 패턴을 제거하는 제5공정, 제2도전층 패턴의 양쪽 측벽에 제2물질층 스페이서를 형성하는 제6공정, 결과물 전면에 제3도전층을 형성하는 제7공정, 및 제3도전층, 제2도전층 패턴 및 제1도전층을 에치백하는 제8공정을 포함하는 것을 특징으로 한다. 따라서, 보다 큰 셀 커패시터 용량을 최소의 면적으로 용이하게 증가시킬 수 있다.A capacitor manufacturing method of a semiconductor memory device is disclosed. The first process includes forming a first conductive layer on a semiconductor substrate, a second process of forming a first material layer on the first conductive layer, and removing the first material layer in a region where the storage electrode is to be formed. The third process of forming the layer pattern, the fourth process of forming the second conductive layer pattern on the sidewalls of the first material layer pattern, the fifth process of removing the first material layer pattern, the both sidewalls of the second conductive layer pattern The sixth step of forming the second material layer spacer, the seventh step of forming the third conductive layer on the entire surface of the resultant, and the eighth step of etching back the third conductive layer, the second conductive layer pattern and the first conductive layer. It is characterized by including. Thus, larger cell capacitor capacity can be easily increased to a minimum area.

Description

반도체 메모리장치의 커패시터 제조방법Capacitor Manufacturing Method of Semiconductor Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2G도는 본 발명에 의한 반도체 메모리장치의 커패시터 제조방법을 설명하기 위해 도시된 단면도들이다.2A to 2G are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor memory device according to the present invention.

Claims (5)

반도체기판 상에 제1도전층을 형성하는 제1공정; 상기 제1도전층 상에 제1물질층을 형성하는 제2공정; 스토리지전극이 형성될 영역의 상기 제1물질층을 제거함으로써 제1물질층 패턴을 형성하는 제3공정; 상기 제1물질층 패턴의 측벽에 제2도전층 패턴을 형성하는 제4공정; 상기 제1물질층 패턴을 제거하는 제5공정; 상기 제2도전층 패턴의 양쪽 측벽에 제2물질층 스페이서를 형성하는 제6공정; 결과물 전면에 제3도전층을 형성하는 제7공정; 및 상기 제3도전층, 제2도전층 패턴 및 제1도전층을 에치백하는 제8공정을 포함하는 것을 특징으로 하는 반도체 메모리장치의 커패시터 제조방법.A first step of forming a first conductive layer on the semiconductor substrate; Forming a first material layer on the first conductive layer; A third step of forming a first material layer pattern by removing the first material layer in a region where a storage electrode is to be formed; A fourth process of forming a second conductive layer pattern on sidewalls of the first material layer pattern; A fifth process of removing the first material layer pattern; A sixth step of forming second material layer spacers on both sidewalls of the second conductive layer pattern; A seventh step of forming a third conductive layer on the entire surface of the resultant product; And an eighth step of etching back the third conductive layer pattern, the second conductive layer pattern, and the first conductive layer. 제1항에 있어서, 상기 제1물질층 및 제2물질층은, 소정의 식각공정에 대해 상기 제1도전층 및 제2도전층을 형성하는 물질과는 그 식각율이 다른 물질을 사용하여 형성되는 것을 특징으로 하는 반도체 메모리장치의 커패시터 제조방법.The method of claim 1, wherein the first material layer and the second material layer are formed using a material having an etching rate different from that of the material forming the first conductive layer and the second conductive layer for a predetermined etching process. Capacitor manufacturing method of a semiconductor memory device, characterized in that. 제1항에 있어서, 상기 제1도전층, 제2도전층 및 제3도전층을 구성하는 물질은, 소정의 식각공정에 대해, 상기 제2물질층을 구성하는 물질과는 그 식각율이 다른 것을 특징으로 하는 반도체 메모리장치의 커패시터 제조방법.The material constituting the first conductive layer, the second conductive layer, and the third conductive layer is different in etch rate from the material constituting the second material layer for a predetermined etching process. Capacitor manufacturing method of a semiconductor memory device, characterized in that. 제2항 또는 제3항 중 어느 한 항에 있어서, 상기 제1도전층, 제2도전층 및 제3도전층을 구성하는 물질로 다결정실리콘을 사용하는 것을 특징으로 하는 반도체 메모리장치의 커패시터 제조방법.4. The method of claim 2 or 3, wherein polycrystalline silicon is used as a material constituting the first conductive layer, the second conductive layer, and the third conductive layer. . 제2항 또는 제3항 중 어느 한 항에 있어서, 상기 제1물질층 및 제2물질층을 구성하는 물질로는 고온산화물, 저온산화물 및 브론-인을 포함한 실리콘(BPSG)등으로 이루어진 군에서 선택된 어느 한 물질을 사용하는 것을 특징으로 하는 반도체 메모리장치의 커패시터 제조방법.According to claim 2 or 3, wherein the material constituting the first material layer and the second material layer in the group consisting of a high temperature oxide, a low temperature oxide and silicon containing Bron-Pin (BPSG), etc. Method of manufacturing a capacitor of a semiconductor memory device, characterized in that using any one selected material. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950008715A 1995-04-13 1995-04-13 Capacitor fabrication method of semiconductor memory device KR0165382B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950008715A KR0165382B1 (en) 1995-04-13 1995-04-13 Capacitor fabrication method of semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950008715A KR0165382B1 (en) 1995-04-13 1995-04-13 Capacitor fabrication method of semiconductor memory device

Publications (2)

Publication Number Publication Date
KR960039369A true KR960039369A (en) 1996-11-25
KR0165382B1 KR0165382B1 (en) 1998-12-15

Family

ID=19412147

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950008715A KR0165382B1 (en) 1995-04-13 1995-04-13 Capacitor fabrication method of semiconductor memory device

Country Status (1)

Country Link
KR (1) KR0165382B1 (en)

Also Published As

Publication number Publication date
KR0165382B1 (en) 1998-12-15

Similar Documents

Publication Publication Date Title
KR950021597A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960039369A (en) Capacitor Manufacturing Method of Semiconductor Memory Device
KR960005846A (en) Manufacturing Method of Semiconductor Device
KR960043190A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960026832A (en) Capacitor Manufacturing Method of Semiconductor Memory Device
KR970054223A (en) Method for forming charge storage electrode of semiconductor device
KR960012499A (en) Method for manufacturing charge storage electrode of capacitor
KR970008596A (en) Capacitor Manufacturing Method Using HSG Mask
KR960043203A (en) Manufacturing Method of Semiconductor Device
KR960043199A (en) Capacitor Manufacturing Method of Semiconductor Memory Device
KR950007101A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970012988A (en) Cylindrical Capacitor Manufacturing Method
KR960043192A (en) Semiconductor Capacitors and Manufacturing Method Thereof
KR970024189A (en) Semiconductor memory device and resistive layer forming method
KR960002789A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960039377A (en) Semiconductor Memory Device Manufacturing Method
KR920001639A (en) Fabrication method of highly integrated memory device of N-MOS cell
KR930015009A (en) DRAM cell manufacturing method
KR970054057A (en) Method of manufacturing capacitors in semiconductor devices
KR960019667A (en) Capacitor Manufacturing Method of Semiconductor Memory Device
KR970030343A (en) Electrode of semiconductor memory device and method of forming same
KR950007104A (en) Manufacturing method of cylindrical capacitor of semiconductor device
KR970052485A (en) Method for manufacturing storage electrodes of capacitor
TW239234B (en) Process of DRAM
KR970054043A (en) Capacitor Manufacturing Method of Semiconductor Memory Device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20060830

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee