KR960035989A - Heat dissipation structure of stacked semiconductor package - Google Patents

Heat dissipation structure of stacked semiconductor package Download PDF

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Publication number
KR960035989A
KR960035989A KR1019950004582A KR19950004582A KR960035989A KR 960035989 A KR960035989 A KR 960035989A KR 1019950004582 A KR1019950004582 A KR 1019950004582A KR 19950004582 A KR19950004582 A KR 19950004582A KR 960035989 A KR960035989 A KR 960035989A
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South Korea
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semiconductor package
subpackage
package
heat dissipation
lead
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KR1019950004582A
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Korean (ko)
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KR0163864B1 (en
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안민철
안승호
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

이 발명은 반도체 장치의 패키징 밀도의 증가의 필요성에 따라 제품화된 적층형 플라스틱 반도체 패키지의 3차원 입체적인 구조 특성상 중앙부위에 적층되는 패키지들의 열방출 및 열분산 특성을 향상시키기 위하여, 반도체 패키지의 하면에서 리드 프레임 패드의 소정 영역이 패키지 몸체와 수직한 방향으로 노출되도록 적어도 하나 이상의 글로브들이 형성되고, 상기 글로브들의 리드 프레임 패드에 열전도성 접착제로 메탈호일들이 장착되며, 상기 반도체 패키지의 외부리드가 패키지 몸체로부터 노출되어 경사지도록 리세스부가 형성된 반도체 패키지의 열방출 구조를 적용하거나; 상기 리드-온-칩 적층형 반도체 패키지 몸체의 상면에서 리드 프레임이 부분 노출되도록 복수개의 리세스부와 다수개의 글로부가 수평방향으로 형성되어 상기 리세스부의 노출된 리드 프레임 상에 열전도성 접착제로 메탄호일들이 접착된 반도체 패키지의 열방출 구조를 적용함으로써, 소자 동작시 발생되는 열을 효과적으로 방출하여 신뢰성을 향상시킬 수 있는 적층형 반도체 패키지의 열방출 구조에 관한 것이다.The present invention is directed to the bottom surface of a semiconductor package in order to improve the heat dissipation and heat dissipation characteristics of the packages stacked in the center due to the three-dimensional three-dimensional structural characteristics of the laminated plastic semiconductor package produced in accordance with the need to increase the packaging density of the semiconductor device At least one glove is formed so that a predetermined area of the frame pad is exposed in a direction perpendicular to the package body, metal foils are mounted on the lead frame pads of the glove with a thermally conductive adhesive, and an outer lead of the semiconductor package is removed from the package body. Applying a heat dissipation structure of the semiconductor package in which the recess portion is formed to be exposed and inclined; A plurality of recesses and a plurality of glows are formed in a horizontal direction so that a lead frame is partially exposed on an upper surface of the lead-on-chip stacked semiconductor package body, and the methane foil is formed of a thermally conductive adhesive on the exposed lead frames of the recesses. The present invention relates to a heat dissipation structure of a laminated semiconductor package that can improve reliability by effectively dissipating heat generated during device operation by applying a heat dissipation structure of a semiconductor package to which the adhesive is bonded.

Description

적층형 반도체 패키지의 열방출 구조Heat dissipation structure of stacked semiconductor package

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제6도는 이 발명에 따른 적층형 반도체 패키지의 열방출 구조에 적용되는 노출된 리드 프레임의 하부 평면도.6 is a bottom plan view of an exposed lead frame applied to the heat dissipation structure of a stacked semiconductor package according to the present invention.

Claims (8)

금속성의 리드 프레임 패드상에 반도체 칩이 장착된 후, 에폭시 몰드 컴 파운드로 인캡슐레이션 된 반도체 패키지에 있어서; 상기 반도체 패키지의 하면에서 리드 프레임 패드의 소정 영역이 패키지 몸체와 수직한 방향으로 노출되도록 적어도 하나 이상의 글로브가 형성되고, 상기 반도체 패키지의 상면에서 패키지 몸체가 편편하지 않도록 적어도 하나 이상의 단턱이 형성되며, 상기 반도체 패키지의 외부리드가 패키지 몸체로부터 노출되어 경사지도록 리세스부가 형성된 것을 특징으로 하는 반도체 패키지의 열방출 구조.A semiconductor package encapsulated with an epoxy mold compound after mounting a semiconductor chip on a metallic lead frame pad; At least one glove is formed on the bottom surface of the semiconductor package to expose a predetermined area of the lead frame pad in a direction perpendicular to the package body, and at least one step is formed on the top surface of the semiconductor package so that the package body is not flat. A heat dissipation structure of a semiconductor package, characterized in that the recess portion is formed so that the outer lead of the semiconductor package is exposed from the package body to be inclined. 인쇄회로기판상에 하면부에 글로부와 상면부의 단턱과 측면부의 리세스부가 각각 형성된 제1부패키지가 실장되고, 상기 제1부패키지의 상면부에 이와 동일한 제2부패키지가 실장되며, 상기 제2부패키지의 상면부에 하면부의 글로브만 형성된 제3부패키지가 차례로 적층 실장된 후, 상기 제1, 제2, 제3 부패키지들의 외부리드들이 솔더에 의해 본딩되어 전기적으로 접속되는 것을 특징으로 하는 적층형 반도체 패키지의 열방출 구조.A first subpackage having a glow portion, a stepped portion and a recess portion at a side portion thereof is mounted on a printed circuit board, and the same second subpackage is mounted on an upper surface of the first subpackage. After the third subpackage, in which only the bottom portion of the second subpackage is formed, is sequentially stacked on the upper surface of the second subpackage, external leads of the first, second and third subpackages are bonded by solder and electrically connected to each other. The heat dissipation structure of the laminated semiconductor package. 금속성의 리드 프레임 패드상에 반도체 칩이 장착된 후, 에폭시 몰드 컴 파운드로 인캡슐레이션 된 반도체 패키지에 있어서; 상기 반도체 패키지의 하면에서 리드 프레임 패드의 소정 영역이 패키지 몸체와 수직한 방향으로 노출되도록 적어도 하나 이사의 글로브들이 형성되고, 상기 글로브들의 리드 프레임패드에 열전도성 접착제로 메탈호일들이 장착되며, 상기 반도체 패키지의 외부리드가 패키지 몸체로부터 노출되어 경사지도록 리세스부가 형성된 것을 특징으로 하는 반도체 패키지의 열방출 구조.A semiconductor package encapsulated with an epoxy mold compound after mounting a semiconductor chip on a metallic lead frame pad; At least one glove is formed on the bottom surface of the semiconductor package such that a predetermined area of the lead frame pad is exposed in a direction perpendicular to the package body, and metal foils are mounted on the lead frame pads of the glove with a thermally conductive adhesive. A heat dissipation structure of a semiconductor package, characterized in that the recess portion is formed so that the outer lead of the package is exposed from the package body to be inclined. 제3항에 있어서, 상기 메탈호일은 고 열전도도를 갖는 카파, 카파 합금, 알루미늄, 알루미늄 합금, 스틸, 스텐레스 스틸중 임의의 군으로 선택되어 형성됨을 특징으로 하는 반도체 패키지의 열방출 구조.The heat dissipation structure of claim 3, wherein the metal foil is selected from any of kappa, kappa alloy, aluminum, aluminum alloy, steel, and stainless steel having high thermal conductivity. 인쇄회로기판상에 하면부의 글로브와 측면부의 리세스부가 형성된 제1부패키지가 실장도고,상기 제1부패키지상에 하면부의 글로브내에 장착된 메탈호일과 측면부의 리세스부가 각각 형성된 제2부패키지가 실장되며, 상기 제2부패키지의 상면부에 하면부의 글로브내에 메탈호일이 장착된 제3부 패키지가 차례로 적층 실장된 후, 상기 제1, 제2, 제3부패키지들의 외부리드들이 솔더에 의해 본딩되어 전기적으로 접속되는 것을 특징으로 하는 적층형 반도체 패키지의 열방출 구조.On the printed circuit board, a first subpackage having a recess on a lower surface and a recess on a side thereof is mounted. A second subpackage on which a metal foil mounted in a globe on a lower surface and a recess on a side of the side is formed on the first subpackage. After the third part package in which the metal foil is mounted in the glove of the lower part is sequentially stacked on the upper surface of the second subpackage, external leads of the first, second and third subpackages are attached to the solder. A heat dissipation structure of a laminated semiconductor package characterized in that the bonding is electrically connected by. 반도체 칩상에 폴리이미드 테이프에 의해 리드 프레임이 접착되고 반도체 칩의 전극패드와 내부리드가 금선으로 연결된 후, 에폭시 몰드 컴파운드로 인캡슐레이션되어 패키지 몸체가 형성된 리드-온-칩 적층형 반도체 패키지에 있어서; 상기 리드-온-칩 적층형 반도체 패키지 몸체의 상면에서 리드 프레임이 부분 노출되도록 복수개의 리세스부와 다수개의 글로부가 수평방향으로 형성된 제1부패키지가 인쇄회로기판상에 실장되고, 상기 제1부패키지상에 이와 동일한 제2부패키지 및 제3부패키지가 실장되며, 상기 제3부패키지상에 글로브가 형성되지 않은 제4부패키지가 차례로 적층 실장된 후, 상기 제1, 제2. 제3 및 제4부패키지의 외브리드들이 솔더에 의해 본딩되어 전기적으로 접속되는 것을 특징으로 하는 리-온-칩형 적층형 반도체 패키지의 열방출 구조.A lead-on-chip stacked semiconductor package in which a lead frame is adhered to a semiconductor chip by a polyimide tape and the electrode pad and the inner lead of the semiconductor chip are connected by gold wire, and then encapsulated with an epoxy mold compound to form a package body; A first subpackage having a plurality of recesses and a plurality of glows in a horizontal direction is mounted on a printed circuit board so that a lead frame is partially exposed from an upper surface of the lead-on-chip stacked semiconductor package body. The same second sub-package and third sub-package are mounted on the package, and the fourth sub-package in which no glove is formed is sequentially stacked on the third sub-package, and then the first and second sub-packages are stacked. A heat dissipation structure of a re-on-chip stacked semiconductor package, characterized in that the external hybrids of the third and fourth subpackages are bonded and electrically connected by solder. 반도체 칩상에 폴리이미드 테이프에 의해 리드 프레임이 접착되고 반도체 칩의 전극패드와 내부리드가 금선으로 연결된 후, 에폭시 몰드 컴파운드로 인캡슐레이션되어 패키지 몸체가 형성된 리드-온-칩 적층형 반도체 패키지에 있어서; 상기 리드-온-칩 적층형 반도체 패키지 몸체의 상면에서 리드 프레임이 부분 노출되도록 복수개의 리세스부와 다수개의 글로브가 수평방향으로 형성되어 상기 리세부의 노출된리드 프레임 상에 열전도성 접착제 메탈호일들이 접착된 제1부패키지가 인쇄호로 기판상에 실장되고, 상기 제1부패키지상에 이와 동일한 제2부패키지 및 제3부패키지가 실장되며, 상기 제3부패키지상에 글로브가 형성되지 않은 제4부패키지가 차례로 적층 실장된 후, 상기 제1, 제2, 제3 및 제4부패키지의 외부리드들이 솔더에 의해 본딩되어 전기적으로 접속되는 것을 특징으로 하는 리드-온-칩형 적층형 반도체 패키지의 열방출 구조.A lead-on-chip stacked semiconductor package in which a lead frame is adhered to a semiconductor chip by a polyimide tape and the electrode pad and the inner lead of the semiconductor chip are connected by gold wire, and then encapsulated with an epoxy mold compound to form a package body; A plurality of recesses and a plurality of globes are formed in a horizontal direction so that the lead frame is partially exposed on the upper surface of the lead-on-chip stacked semiconductor package body, and thermally conductive adhesive metal foils are formed on the exposed lead frame of the recess. A bonded first subpackage is mounted on a substrate by a printing arc, and the same second subpackage and third subpackage are mounted on the first subpackage, and no glove is formed on the third subpackage. After the four subpackages are stacked and sequentially installed, the external leads of the first, second, third and fourth subpackages are bonded by solder and electrically connected to each other. Heat dissipation structure. 제7항에 있어서, 상기 메탈호일은 고 열전도도를 카파, 카파 합금, 알루미늄, 알루미늄 합금, 스틸, 스텐레스 스틸중 임의의 군으로 선택되어 형성됨을 특징으로 하는 반도체 패키지의 열방출 구조.The heat dissipation structure of a semiconductor package according to claim 7, wherein the metal foil is formed by selecting a high thermal conductivity from any one of kappa, kappa alloy, aluminum, aluminum alloy, steel, and stainless steel. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950004582A 1995-03-07 1995-03-07 Heat dispersion structure of stacked package KR0163864B1 (en)

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KR1019950004582A KR0163864B1 (en) 1995-03-07 1995-03-07 Heat dispersion structure of stacked package

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014106051A1 (en) * 2012-12-30 2014-07-03 General Electric Company Heat sink apparatus and method for power semiconductor device module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014106051A1 (en) * 2012-12-30 2014-07-03 General Electric Company Heat sink apparatus and method for power semiconductor device module
US9730365B2 (en) 2012-12-30 2017-08-08 General Electric Company Heat sink apparatus and method for power semiconductor device module

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