JPS6352461A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6352461A JPS6352461A JP61195238A JP19523886A JPS6352461A JP S6352461 A JPS6352461 A JP S6352461A JP 61195238 A JP61195238 A JP 61195238A JP 19523886 A JP19523886 A JP 19523886A JP S6352461 A JPS6352461 A JP S6352461A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- substrate
- electrode
- semiconductor
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 88
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000000853 adhesive Substances 0.000 abstract description 6
- 230000001070 adhesive effect Effects 0.000 abstract description 6
- 238000007789 sealing Methods 0.000 description 17
- 230000002093 peripheral effect Effects 0.000 description 15
- 238000000034 method Methods 0.000 description 13
- 229920005989 resin Polymers 0.000 description 10
- 239000011347 resin Substances 0.000 description 10
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000017260 vegetative to reproductive phase transition of meristem Effects 0.000 description 2
- 206010011224 Cough Diseases 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000009795 derivation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000001007 puffing effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、複数個の半導体チップを高密度でパッケー
ジに封入し、実装効率を向上させた半導体装置に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which a plurality of semiconductor chips are encapsulated in a package at high density to improve packaging efficiency.
電気機器に用いられている半導体装置は、半導体製造技
術の向上に伴いその用途等に応じて、より一層の小型軽
量化、高実装密度化が要請されている。2. Description of the Related Art As semiconductor manufacturing technology improves, semiconductor devices used in electrical equipment are required to be smaller, lighter, and more densely packaged depending on their intended use.
従来、かかる要請に基づいて次のような構成のものが提
案されている０例えば第１４図は、バンク接合形と呼ば
れるもので、バック接合用のＨ型パッケージ凸体１０１
の上下両面に設けた凹部に半導体チップ１０２．１０３
をそれぞれ配置し、基体１０１の表面及び工面に形成さ
れている多数のｉｔパターンと、前記半導体チップ１０
２．１０３の電ｉパッドとをボンディングワイヤ１０４
で接続し、セラミック。Conventionally, the following configurations have been proposed based on such demands. For example, the one shown in FIG.
Semiconductor chips 102 and 103 are placed in the recesses provided on both the upper and lower surfaces of the
are arranged respectively, and a large number of IT patterns formed on the surface and the machined surface of the base body 101 and the semiconductor chip 10 are arranged.
2. Bonding wire 104 with i-pad 103
Connected with ceramic.
金属等の蓋１０５を施して２つの半導体チップを実装し
た半導体装置である。なお、１０６は外部リードである
。This is a semiconductor device in which two semiconductor chips are mounted with a lid 105 made of metal or the like. Note that 106 is an external lead.
第１５図に示すものは、パフケージ基体１１１の一方の
表面に設けた凹部に、複数個の半導体チップ１１２、１
１３．１１４を平面的に並べて配置し、基体表面に形成
されているみ電パターンに、各半導体チップ１１２．１
１３．１１４の電極パッドをボンディングワイヤ１１５
で接続して、苦１１６を設け、一つのパンケージ基体に
複数個の半導体チップを封入したものである。In the device shown in FIG. 15, a plurality of semiconductor chips 112, 1
13.114 are arranged side by side in a plane, and each semiconductor chip 112.1 is placed on the electric pattern formed on the surface of the base body.
13. Bonding wire 115 to electrode pad 114
A plurality of semiconductor chips are encapsulated in one pan-cage base by connecting them to each other and providing a groove 116.
簗１６図に示すものは、パフケージ基体１２１の一方の
表面に２段階状に設けた凹部の最底部に第１の箪導体チ
ップ１２２を配置してその電極パッドを基体１２１の電
極パターンとボンディングワイヤ１２３で接続すると共
に、該第１の半導体チップ１２２上に、それより面積的
に小さい第２の半導体チップ１２４を重ねて接合し、そ
の電極パッドを基体の導電パターンとボンディングワイ
ヤ１２５で接続してパッケージしたものである。In the case shown in Figure 16, a first conductor chip 122 is arranged at the bottom of a recess formed in two stages on one surface of a puff cage base 121, and its electrode pad is connected to the electrode pattern of the base 121 and a bonding wire. 123, a second semiconductor chip 124 smaller in area is stacked and bonded on the first semiconductor chip 122, and its electrode pads are connected to the conductive pattern of the base using bonding wires 125. It is packaged.
また第１７図は、特公昭５９−４４８５１号公報に開示
されているもので、セラミック基体１３１の階段状凹部
に第１の半導体チップ１３２を配置して、その電極パッ
ドを基体の導電パターンとボンディングワイヤで接続し
、該第１の半導体チップ１３２を封止用樹脂１３３を充
填して封止すると共に、蓋１３４を基体凹部の段部に係
止させて固定し、該蓋１３４上には第２の半導体チップ
１３５を固定して、その電極バンドを基体上の導電パタ
ーンとボンディングワイヤで接続し、更にこの第２の半
導体チップ１３５をセラミック等の蓋１３６で被覆して
、一つの基体に２つ半導体チップを実装するようにした
ものである。Further, FIG. 17 is disclosed in Japanese Patent Publication No. 59-44851, in which a first semiconductor chip 132 is placed in a stepped recess of a ceramic base 131, and its electrode pads are bonded to the conductive pattern of the base. The first semiconductor chip 132 is filled with a sealing resin 133 and sealed, and the lid 134 is fixed by being engaged with the stepped part of the base recess. The second semiconductor chip 135 is fixed, its electrode band is connected to the conductive pattern on the base body with a bonding wire, and the second semiconductor chip 135 is further covered with a lid 136 made of ceramic or the like, so that two semiconductor chips 135 are attached to one base body. It is designed to mount two semiconductor chips.
ところが、第１４図に示したものは、パンケージ基本体
１０１がＨ型構造になっているため厚みが大となり、高
密度の実装が困難であり、また外部リードの引き出しが
効率よく行うことができないという欠点がある。また第
１５図に示したものは、多数の半導体チップをパンケー
ジすることができるけれども、実装面積が大となり、高
密度実装ができないし、またワイヤボンディング工程が
複雑になるという欠点がある。However, in the case shown in FIG. 14, since the pancage basic body 101 has an H-shaped structure, the thickness is large, making it difficult to implement high-density mounting, and also making it difficult to draw out external leads efficiently. There is a drawback. Further, although the structure shown in FIG. 15 can pancage a large number of semiconductor chips, it has the disadvantage that the mounting area is large, high-density mounting is not possible, and the wire bonding process is complicated.
第１６図に示したものは、上部の半導体チップ１２４は
下部の半導体チップ１２２の電臘パフドに影響を与えな
いようにｉ！置しなければならないので、上部の半導体
チップ１２４の大きさ、すなわち実装面積に制約を受け
、またワイヤボンディングが２工程となり複雑であると
いう問題点がある。更に第１７図に示したものは、下側
の半導体チップを封止する樹脂１３３を平坦に充填しな
いと、芳１３４が確実にパッケージ基体１３１の凹部の
段部に係合できず、咳蓋１３４への上側の半導体チップ
１３５の取り付けや、ワイヤボンディング工程に支障を
来すという問題点がある。In the case shown in FIG. 16, the upper semiconductor chip 124 is arranged so as not to affect the electrical puffing of the lower semiconductor chip 122. Therefore, there are problems in that the size of the upper semiconductor chip 124, that is, the mounting area is restricted, and wire bonding is complicated because it requires two steps. Furthermore, in the case shown in FIG. 17, unless the resin 133 for sealing the lower semiconductor chip is filled flatly, the cover 134 cannot reliably engage the stepped part of the recess of the package base 131, and the cough lid 134 This poses a problem in that it interferes with the attachment of the upper semiconductor chip 135 and the wire bonding process.
本発明は、従来の複数の半導体チップをパンケージ基体
に封入した半導体装置の上記各問題点を解決するために
なされたもので、実装密度が高く、しかもボンディング
ワイヤの少ない信頼性の高い半導体装置を提供すること
を目的とするものである。The present invention was made in order to solve the above-mentioned problems of the conventional semiconductor device in which a plurality of semiconductor chips are enclosed in a pancage base, and to provide a highly reliable semiconductor device with high packaging density and fewer bonding wires. The purpose is to provide
〔問題点を解決するための手段及び作用〕上記問題点を
解決するため、本発明は、複数個の半導体チップを封入
した半導体装置において、絶縁基体の一方の面に形成し
た導電パターンに接続した第１の半導体チップと、該第
１の半導体チップ上に接合し前記絶縁基体の他方の面に
形成した導電パターンとワイヤボンディングにより接続
した第２の半４体チップとで半導体装置を構成するもの
である。[Means and effects for solving the problems] In order to solve the above problems, the present invention provides a semiconductor device in which a plurality of semiconductor chips are encapsulated, in which a plurality of semiconductor chips are connected to a conductive pattern formed on one surface of an insulating substrate. A semiconductor device is constituted by a first semiconductor chip and a second half-quad chip that is bonded on the first semiconductor chip and connected by wire bonding to a conductive pattern formed on the other surface of the insulating base. It is.
このように構成することにより、２つの半導体チップを
一つのパフケージ基体に高実装密度で封入することが可
能となり、しかもワイヤボンディング工程が少なくなり
、ワイヤ数が少なくて済むので、信頼性の向上を計るこ
とができる。また相互に接続された半導体チップは、互
いに放熱板として機能するので放りヘ効果を向上させる
ことも可能となる。With this configuration, it is possible to encapsulate two semiconductor chips in one puff cage base with high packaging density, and the wire bonding process is reduced, resulting in fewer wires, which improves reliability. It can be measured. Further, since the semiconductor chips connected to each other function as heat sinks, it is also possible to improve the heat dissipation effect.
以下、実施例について説明する。第１図は、本発明に係
る半導体装置の一実施例の概略断面図である０図におい
て、１はエポキシ樹脂、ポリイミド樹脂等からなる平板
状のパッケージ基板で、中央部には半導体チップを配置
するための開孔部２が形成されており、上面には電極パ
ターン３が形成されていて、該電極バタン−３は基板１
の周縁部を通って■面の一部に達するように形成されて
いる。また基体１の裏面にはビームリード４がフィンガ
ー状に前記開孔部２の一部に突出するように形成されて
いる。そして表面の電極パターン３には、後述のボンデ
ィングワイヤ等との接続部を除いて絶縁膜５が施されて
いる。Examples will be described below. FIG. 1 is a schematic cross-sectional view of an embodiment of a semiconductor device according to the present invention. In FIG. An opening 2 is formed for the substrate 1, and an electrode pattern 3 is formed on the upper surface of the substrate 1.
It is formed so that it passes through the peripheral edge of and reaches a part of the surface. Further, on the back surface of the base 1, beam leads 4 are formed in the shape of fingers so as to protrude into a part of the aperture 2. An insulating film 5 is applied to the electrode pattern 3 on the front surface, except for the connection portions with bonding wires and the like, which will be described later.
６は第１の半導体チップで、前記基板１の開孔部２内に
下向きに配置され、その電１バフド又は前記ビームリー
ド４の先端に予め形成されているバンプ７を介して、電
極パッドをビームリード４に通常の熱圧着等の手段によ
り接続し固定されて 。Reference numeral 6 denotes a first semiconductor chip, which is disposed facing downward in the opening 2 of the substrate 1, and has an electrode pad connected thereto via a bump 7 formed in advance at the tip of the buffed electrode 1 or the beam lead 4. It is connected and fixed to the beam lead 4 by ordinary means such as thermocompression bonding.
いる、８は第２の半導体チップで前記第１の半導体チッ
プ６の裏面に絶縁性接着剤により接合されており、その
ｉ極パフドはボンディングワイヤ９により、基板１の表
面電極パターン３に接続されている。 １０は各半導体
チップ６．８と基ｖｉ１の一部を一体的に封止している
、エポキシ樹脂等のモールド材からなるモールド封止部
である。A second semiconductor chip 8 is bonded to the back surface of the first semiconductor chip 6 with an insulating adhesive, and its i-pole puff is connected to the surface electrode pattern 3 of the substrate 1 by a bonding wire 9. ing. Reference numeral 10 denotes a mold sealing portion made of a molding material such as epoxy resin, which integrally seals each semiconductor chip 6.8 and a part of the base vi1.
このように２つの半導体チップをその裏面同士を絶縁性
接着剤で接合して、パッケージ基板ｌの開孔部２内に配
置しているので、全体の厚みを極めて薄くすることがで
きる。また裏面同士の接合なので、互いに半導体チップ
の電極パッドに影響を与えずに装着できる。また一方の
半導体チップ６はワイヤレスボンディングを用いている
ため、ワイヤを少なくし作業性並びに信頼性の向上を計
ることができる。In this way, since the two semiconductor chips are bonded together on their back surfaces with an insulating adhesive and placed in the opening 2 of the package substrate 1, the overall thickness can be made extremely thin. Furthermore, since the back sides are bonded together, they can be attached to each other without affecting the electrode pads of the semiconductor chips. Furthermore, since one semiconductor chip 6 uses wireless bonding, it is possible to reduce the number of wires and improve workability and reliability.
次に第２図（８）〜■）に基づいて、第１図に示した構
成の半導体装置の製造過程について説明する。Next, the manufacturing process of the semiconductor device having the structure shown in FIG. 1 will be explained based on FIGS. 2(8) to 2).
まず第２図式に示すように、中央部に開花部２を有し、
表面から周縁部を通って裏面に達する電極パターン３と
、２面に開花部２の一部に突出するように配置し先端に
バンプ７を形成したビームリード４と、表面に電極パタ
ーン３の接続部を除いて被覆した絶縁膜５とを存するバ
フケージ基板１を用意する０次いで、第２図（Ｂｌに示
すように、第１の半導体チップ６が開花部２内に配置さ
れ、且つ咳チフプ６の電極パッドにバンプ７が対応する
ように、該半導体チップ６に前記基板１を載置し、加勢
圧着部材１１によりバンプ７を介して半導体チップ６と
基板１とを接続固定する。First, as shown in the second diagram, it has a flowering part 2 in the center,
Connecting the electrode pattern 3 from the front surface to the back surface through the peripheral edge, the beam lead 4 which is arranged so as to protrude from a part of the flowering part 2 on the second surface and has a bump 7 formed at the tip, and the electrode pattern 3 on the front surface. Next, as shown in FIG. The substrate 1 is placed on the semiconductor chip 6 so that the bumps 7 correspond to the electrode pads, and the semiconductor chip 6 and the substrate 1 are connected and fixed via the bumps 7 by the pressing member 11.
次に第２図（Ｃ１に示すように、第１の半導体チップ６
の裏面上に第２の半導体チップ８を絶縁性接着剤を介し
て重ね合わせて配置し、第２半導体チップ８のグイボン
ドを行う、この際、第１半導体チンプロ及び基板１が不
安定な場合は、図示のように、これらを治具１２上に配
置して、グイボンド工程を行う、なお１３は治具１２上
に設けた固定枠である。そして前記第２半４体８のグイ
ボンドを行ったのち、ボンディングワイヤ９を用いて第
２半導体チップの電極バンドと電極パターン３とを接続
する。Next, as shown in FIG. 2 (C1), the first semiconductor chip 6
A second semiconductor chip 8 is placed on the back side of the board with an insulating adhesive interposed therebetween, and the second semiconductor chip 8 is bonded. At this time, if the first semiconductor chip and the substrate 1 are unstable, As shown in the figure, these are placed on a jig 12 to perform the Gui bonding process. Reference numeral 13 is a fixed frame provided on the jig 12. After the second half 4 body 8 is bonded, the electrode band of the second semiconductor chip and the electrode pattern 3 are connected using a bonding wire 9.
次いで第２図＋０１に示すように、エポキシ樹脂等のモ
ールド樹脂材を用いて、基板１の一部及び両半導体チッ
プ６．８を一体的にモールドして封止部１０を形成し、
半導体装置を完成する。Next, as shown in FIG. 2+01, a part of the substrate 1 and both semiconductor chips 6.8 are integrally molded using a molding resin material such as epoxy resin to form a sealing part 10,
Complete the semiconductor device.
なお、上記の製造過程において、パンケージ基体として
板状のものを用いたものを示したが、テープキャリヤを
用いても同様に構成することができ、またバンプ７はビ
ームリード４上ではなく半導体チップ上に形成しても同
様に製作することができる。In the above manufacturing process, a plate-shaped pancage substrate is used, but the same configuration can be achieved using a tape carrier, and the bumps 7 are not placed on the beam leads 4 but on the semiconductor chip. It can be manufactured in the same way even if it is formed on top.
第３図は、第１図に示した実施例の変形例を示す断面図
で、この変形例は第１の半導体チンプロより面積の大き
な第２の半導体チップ２１を接着してパッケージしたも
のである９本発明は、２つの半導体チップをその裏面同
士を接合するものであるから、各チップの電極バンドは
互いに影響を受けず、したがってこの変形例のように半
導体チップの相対的な大きさに制約を受けることがなく
なる。FIG. 3 is a sectional view showing a modification of the embodiment shown in FIG. 1, in which a second semiconductor chip 21 having a larger area than the first semiconductor chip is bonded and packaged. 9. Since the present invention connects two semiconductor chips together on their back surfaces, the electrode bands of each chip are not affected by each other, and therefore there is no restriction on the relative size of the semiconductor chips as in this modification. You will no longer receive it.
第４図は、他の実施例を示す断面図で、この実施例は第
１の半導体チップを制御用ＩＣ２２とし、第２の半導体
チップをイメージセンサ２３としたものであり、第２チ
ツプのイメージセンサ２３側のモールド封止部２４は、
透明なモールド樹脂材を用いて形成し、第１チツプの制
御用ＩＣ２２側のモールド封止部２５は、光を遮断でき
る一般的なモールド樹脂材を用いて形成している。なお
、これらの封止部２４．２５は２段階に分けたモールド
工程により形成される。FIG. 4 is a sectional view showing another embodiment. In this embodiment, the first semiconductor chip is a control IC 22, and the second semiconductor chip is an image sensor 23. The mold sealing part 24 on the sensor 23 side is
It is formed using a transparent mold resin material, and the mold sealing part 25 on the control IC 22 side of the first chip is formed using a general mold resin material that can block light. Note that these sealing parts 24 and 25 are formed by a two-step molding process.
第５図八は、第４図に示した実施例の変形例を示す断面
図である。この変形例においては、第１デツプである制
御用ＩＣ２２の表面に、エポキシ系。FIG. 58 is a sectional view showing a modification of the embodiment shown in FIG. 4. In this modification, the surface of the control IC 22, which is the first depth, is coated with epoxy.
ポリイミド系、シリコン系等の遮光できる樹、指を用い
てコーティング１１２６を形成し、該制御用ＩＣ２２の
電極パッド２７となるＡ１表面だけを露出するように、
マスクを用いてエツチングを行い、第５凹（Ｂ）に示す
ような表面を形成する。そしてこの−制御用ＩＣ２２を
、前記実施例と同様にバンプ７を介して電極バンドをビ
ームリード４に接続することにより基板１に固定し、透
明樹脂を用いて透明モールド封止部２８を形成するもの
である。この場合は一回のモールド工程で前記封止部２
８を形成することができる。A coating 1126 is formed using a light-shielding material such as polyimide or silicon, or a finger, so that only the surface of A1, which will become the electrode pad 27 of the control IC 22, is exposed.
Etching is performed using a mask to form a surface as shown in the fifth recess (B). Then, this control IC 22 is fixed to the substrate 1 by connecting the electrode band to the beam lead 4 via the bump 7 as in the previous embodiment, and a transparent mold sealing part 28 is formed using a transparent resin. It is something. In this case, the sealing part 2 can be removed in one molding process.
8 can be formed.
第６図は、他の実施例を示す断面図である。この実施例
は、第４図に示した実施例と同様に、第１半導体チップ
を制御用ＩＣ２２とし、第２半導体チップをイメージセ
ンサ２３としたものであるが、第２半導体チップである
イメージセンサ２３の面積は開孔部２の面積より大とし
、該イメージセンサ２３を制御用ＩＣ２２の裏面に接着
すると共に、該イメージセンサ２３の裏面周縁部を開孔
部２の周縁部表面に接着剤で接着したものである。そし
て表面側には透明樹脂を、裏面側には通常の不透明樹脂
をそれぞれ用いてモールド封止部２４．２５を形成する
ものである。この実施例では、制御用ＩＣ２２への光の
淵れを更に良好に阻止することができる。FIG. 6 is a sectional view showing another embodiment. In this embodiment, like the embodiment shown in FIG. 4, the first semiconductor chip is a control IC 22, and the second semiconductor chip is an image sensor 23, but the second semiconductor chip is an image sensor. The area of 23 is larger than the area of the opening 2, and the image sensor 23 is adhered to the back surface of the control IC 22, and the peripheral edge of the back surface of the image sensor 23 is attached to the peripheral surface of the opening 2 with adhesive. It is glued together. Then, the mold sealing portions 24 and 25 are formed using a transparent resin on the front side and a normal opaque resin on the back side. In this embodiment, it is possible to more effectively prevent light from reaching the control IC 22.
第７図は、更に他の実施例を示す断面図で、これも第４
図に示した実施例と同様に、第１半専体チップを制御用
ＩＣ２２とし、第２半導体チップをイメージセンサ２３
としたものであるが、該イメージセンサ２３の周縁部と
基板１の開孔部２の周縁部表面との間に形成されるギャ
ップに、通常の遮光樹脂を充填して、遮光部２９を形成
したものである。FIG. 7 is a sectional view showing still another embodiment, which is also a fourth embodiment.
Similar to the embodiment shown in the figure, the first semi-dedicated chip is the control IC 22, and the second semiconductor chip is the image sensor 23.
However, the gap formed between the peripheral edge of the image sensor 23 and the peripheral edge surface of the opening 2 of the substrate 1 is filled with a normal light shielding resin to form a light shielding part 29. This is what I did.
この実施例では、上記のように、イメージセンサ２３と
基板１との間に隙間が形成されている場合でも、光の侵
入を良好に阻止することができる。In this embodiment, as described above, even if a gap is formed between the image sensor 23 and the substrate 1, it is possible to effectively prevent light from entering.
以上述べた各実施例は、いずれもモールド樹脂を用いて
モールド封止部を形成したものを示したが、封止部は必
ずしもモールド手段により形成されなければならないも
のではなく、他の手段によっても形成することができる
。第８図は、合成樹脂のポツティングにより封止部３１
．３２を形成した実施例を示す、このボッティング封止
部３１．３２は、それぞれ上側及び下側の２段階に分け
て形成する必要がある。In each of the embodiments described above, the molded sealing portion is formed using mold resin, but the sealing portion does not necessarily have to be formed by molding means, and may be formed by other means. can be formed. FIG. 8 shows a sealing portion 31 formed by potting synthetic resin.
．． The botting sealing portions 31 and 32 shown in this embodiment need to be formed in two stages, upper and lower, respectively.
また第９図に示すように、キャップ３３又は平板状の蓋
３４を用いて、各半導体チップを封止することもできる
。この第９図に示した実施例においては、下側を平板状
の蓋３４を用いて封止したものを示しているが、これは
上側と同様にキャップ状の封止部材を用いて封止しても
よいのは勿論である。Further, as shown in FIG. 9, each semiconductor chip can be sealed using a cap 33 or a flat lid 34. In the embodiment shown in FIG. 9, the lower side is sealed using a flat plate-shaped lid 34, but this is also sealed using a cap-shaped sealing member like the upper side. Of course you can.
次にパッケージ基板における型態パターン及びビームリ
ードの導出方法について説明する。上記各実施例で示し
た電極パターン及びビームリードは第１０図＾、田）の
断面図及び斜視図に示すように配置されているものであ
る。すなわち表面の電極４１は基板周縁部のみ型部４２
を介して基板裏面の一部に設けた電極４３に接続してい
るものである。基板周縁部のＲ電部４２としては平面的
なＲ１部のみならず、スルーホールを半分に切断した半
円筒伏の導電部で構成してもよい。なお４４は裏面に設
けたビームリードである。Next, a method for deriving the mold pattern and beam leads on the package substrate will be explained. The electrode patterns and beam leads shown in each of the above embodiments are arranged as shown in the cross-sectional view and perspective view of FIG. In other words, the electrode 41 on the front surface is connected only to the mold part 42 at the peripheral edge of the substrate.
It is connected to an electrode 43 provided on a part of the back surface of the substrate. The R electrically conductive portion 42 at the peripheral edge of the substrate is not limited to a planar R1 portion, but may be a semicylindrical electrically conductive portion obtained by cutting a through hole in half. Note that 44 is a beam lead provided on the back surface.
第１１図＾、［Ｂ）は、他の電極パターン及びビームリ
ードの導出方法を示す断面図及び斜視図である。FIG. 11 [B] is a cross-sectional view and a perspective view showing another electrode pattern and a method of deriving a beam lead.
この導出方法は、基板周縁部に設けた４電部４５は全て
工面電極４６又はビームリード４７に接続されており、
表面電極４８は基板ｌの中間に設けたスルーホール４９
を介して裏面電極４６と接続されるように構成するもの
である。この電極配置構成は、表裏面逆の配置にしたも
のであっても同様である。In this derivation method, all the four electric parts 45 provided on the peripheral edge of the substrate are connected to the cutting surface electrode 46 or the beam lead 47,
The surface electrode 48 is formed through a through hole 49 provided in the middle of the substrate l.
The structure is such that it is connected to the back electrode 46 via. This electrode arrangement configuration is the same even if the front and back sides are reversed.
第１２図は更に他の導出手段を示す図で、表面電極５０
及び工面電極（又はビームリード）５１が位置をずらし
て配置され、それらがそれぞれ接続されている基板周縁
部の導電部５２．５３が交互に配列されるように構成し
たものである。なお、この構成例は、表面及び裏面電極
にそれぞれ接続されているＲ”１部５１．５２が交互に
規則的に配列したものであるが、このように交互に規則
的に配列しないで、ランダムに配列されるように、表裏
面の電極を配置してもよい。FIG. 12 is a diagram showing still another deriving means, in which the surface electrode 50
The conductive parts 52 and 53 on the peripheral edge of the substrate to which they are connected are arranged alternately. Note that in this configuration example, the R''1 parts 51 and 52 connected to the front and back electrodes are arranged alternately and regularly, but instead of being arranged alternately and regularly like this, they are arranged randomly. The electrodes on the front and back surfaces may be arranged so that they are arranged as follows.
次に表面電極と裏面電極（又はビームリード）の導通方
法について説明する。第１３図へは、スル−ホールを利
用して導通させるものであり、図に示すように、表面電
極５４と裏面電極（又はビームリード）５５とはスルー
ホール５６により接続されている。なお、５７は裏面電
極に接続されない他の表面電極で、基板周縁部の導電部
５８に接続されている。また第１３図ＣＢ＋は、基板周
縁部に設けた導電部により導通させるようにしたもので
あり、図に示すように表面電極５９と裏面電極６０は基
板周縁部の導電部６１により導通接続されている。なお
、６２゜６３は相互に接続されない表面及び裏面電極で
あり、それぞれ基板周縁部のｉｔ部に接続されている。Next, a method of conducting electrical connection between the front electrode and the back electrode (or beam lead) will be explained. In FIG. 13, conduction is achieved using through holes, and as shown in the figure, the front electrode 54 and the back electrode (or beam lead) 55 are connected through the through hole 56. Note that 57 is another front surface electrode that is not connected to the back surface electrode, and is connected to a conductive portion 58 at the peripheral edge of the substrate. Further, in FIG. 13 CB+, conduction is achieved by a conductive part provided at the peripheral edge of the substrate, and as shown in the figure, the front electrode 59 and the back electrode 60 are electrically connected by a conductive part 61 at the peripheral edge of the substrate. There is. Note that reference numerals 62 and 63 denote front and back electrodes that are not connected to each other, and are connected to the IT portion of the peripheral edge of the substrate, respectively.
なお、第１１図（Ａ）、（８１〜第１３図＾、■）に示
したものにおいても、基板周縁部の導電部は、スルーホ
ールを半分に切断した半円筒状の導電部で構成してもよ
いのは勿論である。Note that also in the devices shown in FIG. 11(A) and (FIGS. 81 to 13 ^, ■), the conductive portion at the peripheral edge of the substrate is constituted by a semi-cylindrical conductive portion obtained by cutting the through hole in half. Of course, you can.
以上実施例に基づいて詳細に説明したように、本発明に
よれば、複数の半導体チップを高密度で実装することが
でき、またワイヤボンディング工程が少なくワイヤ数が
少なくて済むので、信頼性の向上を計ることができる。As described above in detail based on the embodiments, according to the present invention, a plurality of semiconductor chips can be mounted at high density, and the number of wires can be reduced due to fewer wire bonding steps, resulting in improved reliability. You can measure your improvement.
また、半導体チップは相互に接合されているので、互い
に放熱板として機能し放熱効果を向上させることができ
る。Further, since the semiconductor chips are bonded to each other, they each function as a heat sink, and the heat dissipation effect can be improved.
第１図は、本発明に係る半導体装置の一実施例の概略断
面図、第２図（９）〜■）は、第１図に示した半導体装
置の製造過程を示す図、第３図は、第１図に示した実施
例の変形例を示す図、第４図は、他の実施例を示す断面
図、第５図へは、第４図に示した実施例の変形例を示す
断面図、第５図（Ｂｌは、その変形例における第１の半
導体チップの表面を示す平面図、第６図及び第７図は、
それぞれ他の実施例を示す断面図、第８図及び第９図は
、それぞれ異なる封止手段を用いた半導体装置を示す断
面図、第１０図＾、！Ｂ）は、パッケージ基板の電極パ
ターン及びビームリードの導出方法を示す断面図及び斜
視図、第１１図へ、（Ｂ）は、他の電極パターン及びビ
ームリードの導出方法を示す断面図及び斜視図、第１２
図は、更に他の電極パターン及びビームリードの導出方
法を示す斜視図、第１３図（Ａ１．ｔＥｌは、表面電極
と裏面電極又はビームリードとの導通手段を示す斜視図
、第１４図〜第１７図は、従来の＊数個の半導体チップ
を実装した半導体装置を示す断面図である。
図において、１はパンケージ基板、２は開孔部、３は電
極パターン、４はビームリード、５は絶縁膜、６は第１
の半導体チップ、７はバンプ、８は第２の半導体チップ
、９はポンディングワイヤ、１０はモールド封止部を示
す。
特許出願人 オリンパス光学工業株式会社第１図
第３図
第４図
第２図
（Ａ）
ＣＢ）
（Ｄ）
第５図
（Ａ） （Ｂ）第６図
第７図
第８図
第９図
諷
第１０図
（Ａ） （Ｂ）第１１図
（Ａ） （Ｂ）藺
ｂ
第１２図
第１３図
（Ａ）
ＣＢ）
第１４図FIG. 1 is a schematic sectional view of an embodiment of a semiconductor device according to the present invention, FIG. 2 (9) to (■)) are diagrams showing the manufacturing process of the semiconductor device shown in FIG. , FIG. 4 is a sectional view showing another embodiment, and FIG. 5 is a sectional view showing a modification of the embodiment shown in FIG. 4. , FIG. 5 (Bl is a plan view showing the surface of the first semiconductor chip in the modified example, FIGS. 6 and 7 are
FIGS. 8 and 9 are cross-sectional views showing other embodiments, respectively, and FIG. 10 is a cross-sectional view showing semiconductor devices using different sealing means, respectively! B) is a cross-sectional view and a perspective view showing the electrode pattern of the package substrate and a method for leading out the beam lead, and FIG. 11 is a cross-sectional view and a perspective view showing another electrode pattern and a method for leading out the beam lead. , 12th
The figures are a perspective view showing still another electrode pattern and a method for deriving a beam lead, and FIG. Figure 17 is a cross-sectional view showing a conventional semiconductor device mounted with several semiconductor chips. In the figure, 1 is a pan cage substrate, 2 is an opening, 3 is an electrode pattern, 4 is a beam lead, and 5 is a Insulating film, 6 is the first
, 7 is a bump, 8 is a second semiconductor chip, 9 is a bonding wire, and 10 is a mold sealing part. Patent applicant: Olympus Optical Industry Co., Ltd. Figure 1 Figure 3 Figure 4 Figure 2 (A) CB) (D) Figure 5 (A) (B) Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 (A) (B) Figure 11 (A) (B) Figure 12 Figure 13 (A) CB) Figure 14
Claims (1)
絶縁基体の一方の面に形成した導電パターンに接続した
第１の半導体チップと、該第１の半導体チップ上に接合
し前記絶縁基体の他方の面に形成した導電パターンとワ
イヤボンディングにより接続した第２の半導体チップと
を備えていることを特徴とする半導体装置。In a semiconductor device encapsulating multiple semiconductor chips,
a first semiconductor chip connected to a conductive pattern formed on one surface of the insulating substrate; and a first semiconductor chip bonded on the first semiconductor chip and connected to the conductive pattern formed on the other surface of the insulating substrate by wire bonding. 1. A semiconductor device comprising: 2 semiconductor chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61195238A JPS6352461A (en) | 1986-08-22 | 1986-08-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61195238A JPS6352461A (en) | 1986-08-22 | 1986-08-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6352461A true JPS6352461A (en) | 1988-03-05 |
Family
ID=16337781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61195238A Pending JPS6352461A (en) | 1986-08-22 | 1986-08-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6352461A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0220522U (en) * | 1988-07-25 | 1990-02-09 | ||
| US5313367A (en) * | 1990-06-26 | 1994-05-17 | Seiko Epson Corporation | Semiconductor device having a multilayer interconnection structure |
| US5563773A (en) * | 1991-11-15 | 1996-10-08 | Kabushiki Kaisha Toshiba | Semiconductor module having multiple insulation and wiring layers |
| JPH1056104A (en) * | 1996-06-24 | 1998-02-24 | Internatl Business Mach Corp <Ibm> | Semiconductor device package and method for assembling the same |
| US6445594B1 (en) | 2000-02-10 | 2002-09-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having stacked semiconductor elements |
| KR100457424B1 (en) * | 2000-12-26 | 2004-11-16 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and its manufacturing method |
| US6870249B2 (en) | 2002-12-24 | 2005-03-22 | Oki Electric Industry Co., Ltd. | Semiconductor device and manufacturing method thereof |
| JP2008294478A (en) * | 2008-08-25 | 2008-12-04 | Panasonic Electric Works Co Ltd | Method for connecting terminals between chips, circuit board fabricated using it, and fire detector equipped with it |
-
1986
- 1986-08-22 JP JP61195238A patent/JPS6352461A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0220522U (en) * | 1988-07-25 | 1990-02-09 | ||
| US5313367A (en) * | 1990-06-26 | 1994-05-17 | Seiko Epson Corporation | Semiconductor device having a multilayer interconnection structure |
| US5563773A (en) * | 1991-11-15 | 1996-10-08 | Kabushiki Kaisha Toshiba | Semiconductor module having multiple insulation and wiring layers |
| JPH1056104A (en) * | 1996-06-24 | 1998-02-24 | Internatl Business Mach Corp <Ibm> | Semiconductor device package and method for assembling the same |
| US5872397A (en) * | 1996-06-24 | 1999-02-16 | International Business Machines Corporation | Semiconductor device package including a thick integrated circuit chip stack |
| US6445594B1 (en) | 2000-02-10 | 2002-09-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having stacked semiconductor elements |
| KR100457424B1 (en) * | 2000-12-26 | 2004-11-16 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and its manufacturing method |
| US6870249B2 (en) | 2002-12-24 | 2005-03-22 | Oki Electric Industry Co., Ltd. | Semiconductor device and manufacturing method thereof |
| JP2008294478A (en) * | 2008-08-25 | 2008-12-04 | Panasonic Electric Works Co Ltd | Method for connecting terminals between chips, circuit board fabricated using it, and fire detector equipped with it |
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