KR960026376A - Method of forming planarization insulating film - Google Patents

Method of forming planarization insulating film Download PDF

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Publication number
KR960026376A
KR960026376A KR1019940035739A KR19940035739A KR960026376A KR 960026376 A KR960026376 A KR 960026376A KR 1019940035739 A KR1019940035739 A KR 1019940035739A KR 19940035739 A KR19940035739 A KR 19940035739A KR 960026376 A KR960026376 A KR 960026376A
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KR
South Korea
Prior art keywords
forming
insulating film
bpsg film
planarization insulating
film
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Application number
KR1019940035739A
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Korean (ko)
Other versions
KR0140812B1 (en
Inventor
유경식
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940035739A priority Critical patent/KR0140812B1/en
Publication of KR960026376A publication Critical patent/KR960026376A/en
Application granted granted Critical
Publication of KR0140812B1 publication Critical patent/KR0140812B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 기판상에 저농도의 BPSG막을 형성하는 단계; 상기 BPSG막상에 Ge 이온을 주입하는 단계; 및 열처리 공정을 통해 상기 BPSG막을 플로우(Flow) 시켜 평탄화시키는 단계를 포함하는 것을 특징으로 하는 평탄화 절연막 형성 방법에 관한것으로, 전도막 간의 우수한 평탄화를 갖으면서 결함이 발생되지 않는 층간절연막을 형성함으로써, 고집적화로 인한 기판의 토포로지를 완화시켜 제조 공정 상의 용이함과 소자의 특성을 향상 시키는 효과가 있다.The present invention comprises the steps of forming a low concentration of BPSG film on the substrate; Implanting Ge ions onto the BPSG film; And forming a planarization insulating film by flowing the BPSG film through a heat treatment process, thereby forming an interlayer insulating film having excellent planarization between conductive films and free of defects. By reducing the topology of the substrate due to high integration, there is an effect of improving the ease of manufacturing process and device characteristics.

Description

평탄화 절연막 형성 방법Method of forming planarization insulating film

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1C도는 본 발명의 일실시예에 따른 평탄화절연막 형성 공정도.1C is a process chart of forming a planarization insulating film according to an embodiment of the present invention.

Claims (3)

평탄화 절연막 형성 방법에 있어서; 기판상에 저농도의 BPSG막을 형성하는 단계; 상기 BPSG막상에 Ge이온을 주입하는 단계; 및 열처리 공정을 통해 상기 BPSG막을 플로우(Flow) 시켜 평탄화시키는 단계를 포함하는 것을 특징으로 하는 평탄화 절연막 형성 방법.A method of forming a planarization insulating film; Forming a low concentration BPSG film on the substrate; Implanting Ge ions onto the BPSG film; And planarizing the flow of the BPSG film through a heat treatment process. 제1항에 있어서; 상기 저농도의 BPSG막은 B과 P이 농도가 각각 4∼5wt%가 되도록 형성하는 것을 특징으로하는 평탄화 절연막 형성 방법.The method of claim 1; The low concentration BPSG film is a planarization insulating film forming method, characterized in that the B and P are formed so that the concentration is 4 to 5wt%, respectively. 제1항에 있어서; 상기 Ge 이온주입은 BPSG막의 표면에서 1/3 정도의 깊이가 Rp(Projected Range)값이 되도록 이온주입하는 것을 특징으로 하는 평탄화 절연막 형성 방법.The method of claim 1; Wherein the Ge ion implantation is ion implanted such that a depth of about 1/3 of the surface of the BPSG film becomes an Rp (Projected Range) value. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940035739A 1994-12-21 1994-12-21 Fabrication method of planar-isolation rilm KR0140812B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940035739A KR0140812B1 (en) 1994-12-21 1994-12-21 Fabrication method of planar-isolation rilm

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940035739A KR0140812B1 (en) 1994-12-21 1994-12-21 Fabrication method of planar-isolation rilm

Publications (2)

Publication Number Publication Date
KR960026376A true KR960026376A (en) 1996-07-22
KR0140812B1 KR0140812B1 (en) 1998-07-15

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ID=19402747

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940035739A KR0140812B1 (en) 1994-12-21 1994-12-21 Fabrication method of planar-isolation rilm

Country Status (1)

Country Link
KR (1) KR0140812B1 (en)

Also Published As

Publication number Publication date
KR0140812B1 (en) 1998-07-15

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