KR0140812B1 - Fabrication method of planar-isolation rilm - Google Patents
Fabrication method of planar-isolation rilmInfo
- Publication number
- KR0140812B1 KR0140812B1 KR1019940035739A KR19940035739A KR0140812B1 KR 0140812 B1 KR0140812 B1 KR 0140812B1 KR 1019940035739 A KR1019940035739 A KR 1019940035739A KR 19940035739 A KR19940035739 A KR 19940035739A KR 0140812 B1 KR0140812 B1 KR 0140812B1
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- Prior art keywords
- bpsg film
- film
- forming
- planarization
- heat treatment
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- 238000000034 method Methods 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title abstract description 4
- 238000002955 isolation Methods 0.000 title 1
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 29
- 238000010438 heat treatment Methods 0.000 claims abstract description 13
- 150000002500 ions Chemical class 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000005468 ion implantation Methods 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 230000007547 defect Effects 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 2
- 230000010354 integration Effects 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 description 17
- 230000004888 barrier function Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000010410 layer Substances 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000002244 precipitate Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910021480 group 4 element Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 210000003141 lower extremity Anatomy 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 기판상에 저농도의 BPSG막을 형성하는 단계; 상기 BPSG막상에 Ge 이온을 주입하는 단계; 및 열처리 공정을 통해 상기 BPSG막을 플로우(Flow) 시켜 평탄화시키는 단계를 포함하는 것을 특징으로 하는 평탄화 절연막 형성 방법에 관한 것으로, 전도막 간의 우수한 평탄화를 갖으면서 결함이 발생되지 않는 층간절연막을 형성함으로써, 고집적화로 인한 기판의 토포로지를 완화시켜 제조 공정 상의 용이함과 소자의 특성을 향상 시키는 효과가 있다.The present invention comprises the steps of forming a low concentration of BPSG film on the substrate; Implanting Ge ions onto the BPSG film; And forming a planarization insulating film by flowing the BPSG film through a heat treatment process, thereby forming an interlayer insulating film having excellent planarization between conductive films and no defects. By reducing the topology of the substrate due to high integration, there is an effect of improving the ease of manufacturing process and device characteristics.
Description
제1A도 내지 제1C도는 본 발명의 일실시예에 따른 평탄화 절연막 형성 공정도.1A to 1C are planarization insulating film formation process diagrams according to an embodiment of the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11:폴리실리콘 배선 12:확산방지막11: polysilicon wiring 12: diffusion barrier
13:저농도 BPSG막 14:이온주입13: Low concentration BPSG film 14: Ion injection
15:이온주입된 Ge 13':펑탄화된 GeBPSG막15: Ion-infused Ge 13 ': Punched GeBPSG Film
본 발명은 반도체 제조 기술 중에서 폴리실리콘 배선 층간의 평탄화 절연막 형성 방법에 관한 것으로, BPSG막의 불순물(Dopant, Boron Phoshporus) 농도를 낮추고, 이온주입법(Ion Implantation)으로 제3의 불순물을 첨가하여 평탄화 열처리를 함으로써 평탄화된 층간절연막(Inter Poly Oxide)을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a planarization insulating film between polysilicon wiring layers in semiconductor manufacturing technology, and to lowering the concentration of impurities (Dopant, Boron Phoshporus) in a BPSG film and adding a third impurity by ion implantation. The present invention relates to a method of forming a planarized interlayer insulating film (Inter Poly Oxide).
폴리실리콘 배선 층간 절연과 평탄화를 위해 사용하는 BPSG막은 불순물의 양이 많을수록 열처리 후의 평탄각(Flow Angle)이 우수하다.The BPSG film used for polysilicon wiring interlayer insulation and planarization has an excellent flow angle after heat treatment as the amount of impurities increases.
그러나, BPSG막은 대기 방치시 수분 흡수에 의해 막질이 불안정하고 평탄화 열처리시 불순물에 의한 결정 석출물(Crystal Defect)의 발생 가능성이 높아지며 열처리 공정시 불순물이 확산되어 하지재료가 침식 당하기 때문에 확산방지막의 두께도 증가하여야 하고 열처리 온도를 높이게 되면 접합깊이(Junction Depth)를 유지하기 힘들어지게 된다.However, the BPSG film has an unstable film quality due to moisture absorption when left in the air, and a high probability of occurrence of crystal defects due to impurities during planarization heat treatment. Increasing the temperature and increasing the heat treatment temperature makes it difficult to maintain the junction depth.
특히, 최근 관심이 집중되고 있는 기상화학증착법(APCVD)으로 증착된 03-TEOS BPSG막은 플라즈마 화학 증착법(PECVD)으로 증착한 BPSG막이나 저압 화학증착법(LPCVD)으로 증착한 BPSG막에 비해 층덮힘성(Step Coverage)과 평탄화율이 우수하지만 수분 흡수성도 매우 크다고 알려져 있다.In particular, the 03-TEOS BPSG film deposited by the APCVD (Petrochemical Vapor Deposition) has recently been focused on the layer coverability compared to the BPSG film deposited by the Plasma Chemical Vapor Deposition (PECVD) or the BPSG film deposited by the Low Pressure Chemical Vapor Deposition (LPCVD). Although it has excellent step coverage and flattening rate, it is known to have very high water absorption.
상기와 같이 불순물에 의한 결정 석출물의 생성을 억제하고 수분 흡습성을 억제하기 위해서 저농도 BPSG막을 사용하면 불순물의 양이 감소하여 같은 조건의 열처리 시 고농도 BPSG막에 비해 평탄화 율이 나빠지게 되고, 열처리 온도를 높이면 접합에 악영향을 주게 된다.As described above, when the low concentration BPSG film is used to suppress the formation of crystal precipitates due to impurities and the moisture hygroscopicity, the amount of impurities decreases, resulting in poor planarization rate compared to the high concentration BPSG film under the same conditions. Increasing it will adversely affect the joint.
따라서, 본 발명은 펑탄화율이 높으며, 수분흡수성이 적은 평탄화 절연막 형성 방법을 제공함을 그 목적으로 한다.Accordingly, an object of the present invention is to provide a method for forming a planarization insulating film having a high puncturing rate and low water absorption.
상기 목적을 달성하기 위하여 본 발명은 평탄화 절연막 형성 방법에 있어서; 기판상에 저농도의 BPSG막을 형성하는 단계; 상기 BPSG막상에 Ge 이온을 주입하는 단계; 및 열처리 공정을 통해 상기 BPSG막을 플로우(Flow) 시켜 평탄화시키는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for forming a planarization insulating film; Forming a low concentration BPSG film on the substrate; Implanting Ge ions onto the BPSG film; And planarizing the flow of the BPSG film through a heat treatment process.
본 발명의 기술적 원리는 이온주입법으로 Ge을 주입하여 저농도 BPSG막의 평탄화율을 증가시키느 원리이다. Ge이 주입된 부분은 GeBPSG막이 형성되어 그래스(Glass)의 연화점을 낮추는 역할을 한다.The technical principle of the present invention is to increase the planarization rate of low concentration BPSG film by implanting Ge by ion implantation. The Ge-implanted portion forms a GeBPSG film, which serves to lower the softening point of the glass.
일반적으로 GeBPSG막은 기존의 BPSG막에 비해 평탄화 특성이 우수한 것으로 알려저 있다. 이온 주입시 에너지를 조절하게 되며 하지 재료가 침식당하지 않은 상태에서 우리가 원하는 만큼의 불순물을 첨가할 수 있다.In general, GeBPSG film is known to have excellent planarization characteristics compared to the conventional BPSG film. Ion implantation controls energy and we can add as much impurities as we want without the underlying material being eroded.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제1A도 내지 제1C도는 본 발명의 일실시예에 따른 평탄화절연막 형성 공정도이다.1A through 1C are process charts for forming a planarization insulating film according to an embodiment of the present invention.
먼저, 제1a도는 폴리실리콘 배선(11)을 형성하고 확산 방지막(12)을 증착한 다음, B 및 P의 농도가 적은 저농도 BPSG막(13)을 증착한 상태에서 Ge 이온을 이온주입(14)하는 상태의 단면도로서, 확산방지막(12)의 두께는 고농도 BPSG막을 증착할 때보다 낮출 수 있다.First, in FIG. 1A, the polysilicon wiring 11 is formed, the diffusion barrier layer 12 is deposited, and then Ge ions are implanted 14 in the state of depositing the low concentration BPSG layer 13 having a low B and P concentration. As a cross-sectional view of the state, the thickness of the diffusion barrier 12 may be lower than that of depositing a high concentration BPSG film.
BPSG막의 두께는 평탄화에 필요한 만큼의 충분한 두께로 증착을 하고 이때 불순물의 농도는 B과 P을 각각 4∼5wt%로 유지한다. 이온주입(14)하는 불순물은 Ge이고, 불순물의 양(Dose)은 1E15∼5E16/cm3으로 한다. 가속에너지는 40∼70keV범위로, 증착된 막의 표면에서 1/3 정도의 깊이가 Rp(Projected Range, 불순물이 가장 많이 분포하는 깊이)값이 되도록 조절한다. 에너지가 강할 경우 폴리실리콘 배선구조에 결함(Defect)을 유발할 수 있기 때문이다. Rp값이 작더라도 일부분은 하지에 영향을 줄 수 있다. 이온주입시 가해지는 많은 양의 에너지는 BPSG막과의 충돌시 열로 전환되어 BPSG막에 흡착되어 있던 수분을 탈착시키는 역할을 하게 되고, 표면은 순간 열처리 공정(Repid Thermal Anneal)을 수행한 것과 같은 상태를 유지하여 수분 흡수를 억제한다. 그리고 이온 주입된 영역은 비정질 상태가 심화되어 평탄화 열처리시 필요한 표면 에너지(surface energy)가 증가하므로 평탄화율이 증가하게 된다.The thickness of the BPSG film is deposited to a thickness sufficient for planarization, and the concentrations of impurities maintain B and P at 4 to 5 wt%, respectively. The impurity implanted in the ion implantation 14 is Ge, and the amount (Dose) of the impurity is 1E15 to 5E16 / cm 3 . The acceleration energy is in the range of 40 to 70 keV, and the depth of 1/3 of the depth of the deposited film is adjusted to be the value of R p (Projected Range). This is because a strong energy can cause defects in the polysilicon interconnection structure. Even small values of R p may affect the lower limbs. A large amount of energy applied during ion implantation is converted into heat when colliding with the BPSG film to desorb water adsorbed on the BPSG film, and the surface is in the same state as the Rapid Thermal Anneal. To keep the water absorbed. In the ion implanted region, the amorphous state is deepened, and thus the planarization rate is increased because the surface energy required for the planarization heat treatment is increased.
이어서, 제1b도는 이온 주입 후의 불순물의 분포를 나타내는 것으로, 평판에 이온 주입 할 때와는 달리 토폴로지(Topology)가 존재하는 상태에서 이온 주입을 하게되면 가속된 불순물 Ge(15)의 진행방향이 도면에 도시된 바와 같이 단차진 부위의 측면으로 바뀌게 되어 측벽을 따라 불순물의 분포가 잡중되게 되므로 평탄화 열처리시 측벽부분의 연화점을 주변보다 낮게 하여 평탄화를 촉진하게 된다. 주입된 불순물은 막과의 충돌시 에너지를 잃어버려 막내의 다른 원자와 결합하지 않고 순수한 상태로 존재하게 된다.Next, FIG. 1B shows the distribution of impurities after ion implantation. When ion implantation is performed in a state where topology is present, unlike when ion implantation is performed on a flat plate, the advancing direction of the accelerated impurity Ge 15 is shown in the figure. As shown in FIG. 2, the impurity distribution is concentrated along the sidewalls, and the softening point of the sidewall portion is lower than the periphery during the planarization heat treatment to promote planarization. The implanted impurities lose their energy when they collide with the membrane and remain in a pure state without binding to other atoms in the membrane.
제1c도는 열처리 공정을 통해 GeBPSG막(13')을 평탄화시킨 상태이다. 이때, 독립된 상태로 존재하던 Ge은 평탄화 열처리시 산화되어 다른 불순물과 마찬가지로 안정화된 상태로 존재하게 된다. Ge이 열처리시 열 확산되어 막 전면에 고루 분포하게 되더라도 양이 너무 작아서 확산 방지막이나 Poly Si 배선 구조에 별 영향은 주지 못하고, 실제로 Ge가 침투한다 하여도 Si 와 같은 4족 원소이기 때문에 무시할 수 있다. 또한 BPSG막의 불순물 농도가 낮기 때문에 평탄화 열처리시 불순물의 가스 방출(Out Gasing)에 의한 결정 석출물의 생성 가능성은 매우 줄어들게 되고 BPSG막 평탄화 열처리 후 증착하는 확산 방지막의 두께도 감소시킬 수 있게 된다.In FIG. 1C, the GeBPSG film 13 'is planarized through a heat treatment process. At this time, Ge, which existed in an independent state, is oxidized during the planarization heat treatment to exist in a stabilized state like other impurities. Although Ge is thermally diffused during heat treatment and evenly distributed throughout the film, the amount is so small that it does not affect the diffusion barrier or Poly Si wiring structure, and even if Ge actually penetrates, it can be ignored because it is a Group 4 element such as Si. . In addition, since the impurity concentration of the BPSG film is low, the possibility of the formation of crystal precipitates due to the outgasing of impurities during the planarization heat treatment is greatly reduced, and the thickness of the diffusion barrier film deposited after the BPSG film planarization heat treatment can be reduced.
이상, 상기 설명과 같은 본 발명은 전도막 간의 우수한 평탄화를 갖으면서 결함이 발생되지 않는 층간절연막을 형성함으로써, 고집적화로 인한 기판의 토포로지를 완화시켜 제조 공정 상의 용이함과 소자의 특성을 향상 시키는 효과가 있다.As described above, the present invention has the effect of improving the ease of manufacturing process and device characteristics by mitigating the topology of the substrate due to high integration by forming an interlayer insulating film having excellent planarization between the conductive films and no defects. There is.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940035739A KR0140812B1 (en) | 1994-12-21 | 1994-12-21 | Fabrication method of planar-isolation rilm |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940035739A KR0140812B1 (en) | 1994-12-21 | 1994-12-21 | Fabrication method of planar-isolation rilm |
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| Publication Number | Publication Date |
|---|---|
| KR960026376A KR960026376A (en) | 1996-07-22 |
| KR0140812B1 true KR0140812B1 (en) | 1998-07-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940035739A KR0140812B1 (en) | 1994-12-21 | 1994-12-21 | Fabrication method of planar-isolation rilm |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0140812B1 (en) |
-
1994
- 1994-12-21 KR KR1019940035739A patent/KR0140812B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR960026376A (en) | 1996-07-22 |
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