KR960026297A - Manufacturing method of fine pattern of semiconductor device - Google Patents

Manufacturing method of fine pattern of semiconductor device Download PDF

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Publication number
KR960026297A
KR960026297A KR1019940037486A KR19940037486A KR960026297A KR 960026297 A KR960026297 A KR 960026297A KR 1019940037486 A KR1019940037486 A KR 1019940037486A KR 19940037486 A KR19940037486 A KR 19940037486A KR 960026297 A KR960026297 A KR 960026297A
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KR
South Korea
Prior art keywords
pattern
layer
oxide
spacer
forming
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Application number
KR1019940037486A
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Korean (ko)
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KR0140485B1 (en
Inventor
김근태
이승우
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김주용
현대전자산업 주식회사
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Priority to KR1019940037486A priority Critical patent/KR0140485B1/en
Publication of KR960026297A publication Critical patent/KR960026297A/en
Application granted granted Critical
Publication of KR0140485B1 publication Critical patent/KR0140485B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체소자의 미세패턴 제조방법에 관한 것으로서, 피식각층상에 산화막 패턴을 형성하고, 상기 산화막 패턴의측벽에 산화막 스페이서를 형성한 후, 상기 산화막 스페이서 사이의 노출되어 있는 피식각층상에 질화막 패턴을 형성함,상기 산화막 패턴과 스페이서를 제거하며, 상기 질하막 패턴을 마스크로 피식각층을 제거하여 미세패턴을 형성하였으므로, 산화막 패턴의 높이에 따른 스페이서의 폭을 조절하여 감광막패턴의 분해능 한계치 이하의 미세패턴을 용이하게 형성하며 공정여유도가 증가되고 소자의 고집적화에 유리하며 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a fine pattern of a semiconductor device, wherein an oxide film pattern is formed on an etched layer, an oxide film spacer is formed on a side wall of the oxide pattern, and a nitride film is exposed on the exposed etching layer between the oxide film spacers. A pattern is formed, and the oxide layer pattern and the spacer are removed, and the etching pattern layer is removed using the sublingual layer pattern as a mask, thereby forming a fine pattern. Thus, by adjusting the width of the spacer according to the height of the oxide layer pattern, the resolution limit of the photoresist layer pattern is less than or equal to It is possible to easily form the fine pattern of the process, the process margin is increased, it is advantageous to the high integration of the device, it is possible to improve the process yield and the reliability of the device operation.

Description

반도체소자의 미세패턴 제조방법Manufacturing method of fine pattern of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1f도는 본 발명에 따른 반도체소자의 미세패턴 제조공정도.Figure 1f is a process diagram of fine pattern manufacturing of the semiconductor device according to the present invention.

Claims (3)

예정된 구조의 반도체기판상에 피식각층을 형성하는공정과, 상기 피식각층상에 예정된 두께의 산화막 패턴들을 형성하는 공정과, 상기 산화막 패턴의 측벽에 산화막 스페이서를 형성하여 상기 피식각층에서 패턴으로 예정되어 있는 부분을 노출시키는 공정과, 상기 산화막과 스페이서에 의해 노출되어 있는 피식각층상에 질화막 패턴을 형성하는 공정과, 상기 산화막 패턴과 스페이서를 제거하는 공정과, 상기 질화막 패턴을 마스크로 노출되어 있는 피식각층을 제거하여피식각층 패턴을 형성하는 공정을 구비하는 반도체소자의 미세패턴 제조방법.Forming an etched layer on a semiconductor substrate having a predetermined structure, forming an oxide pattern of a predetermined thickness on the etched layer, and forming an oxide spacer on a sidewall of the oxide pattern to form a pattern in the etched layer Exposing a portion having a portion thereof; forming a nitride film pattern on the etched layer exposed by the oxide film and the spacer; removing the oxide film pattern and the spacer; and exposing the nitride film pattern with a mask. A method of manufacturing a fine pattern of a semiconductor device, comprising the step of removing each layer to form an etched layer pattern. 제1항에 있어서, 상기 피식각층이 다결정실리콘층이나 금속층인 것을 특징으로 하는 반도체소자의 미세패턴 제조방법.The method of claim 1, wherein the etched layer is a polysilicon layer or a metal layer. 제1항에 있어서, 상기 질화막 패턴 형성 공정을 폴리싱이나 전ㅂ면 식각방법으로 실시하는 것을 특징으로하는 반도체소자의 미세패턴 제조방법.The method of claim 1, wherein the nitride film pattern forming process is performed by polishing or front surface etching. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940037486A 1994-12-27 1994-12-27 A method manufacturing fine pattern of semiconductor device KR0140485B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940037486A KR0140485B1 (en) 1994-12-27 1994-12-27 A method manufacturing fine pattern of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940037486A KR0140485B1 (en) 1994-12-27 1994-12-27 A method manufacturing fine pattern of semiconductor device

Publications (2)

Publication Number Publication Date
KR960026297A true KR960026297A (en) 1996-07-22
KR0140485B1 KR0140485B1 (en) 1998-07-15

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KR1019940037486A KR0140485B1 (en) 1994-12-27 1994-12-27 A method manufacturing fine pattern of semiconductor device

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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101002928B1 (en) * 2003-11-29 2010-12-27 주식회사 하이닉스반도체 Fabricating method of minute line in semiconductor device
KR100640525B1 (en) 2004-12-29 2006-10-31 동부일렉트로닉스 주식회사 Method for defining the metal line of semiconductor device
KR100861172B1 (en) * 2006-09-12 2008-09-30 주식회사 하이닉스반도체 Method for Forming Fine Patterns of Semiconductor Devices
US7790357B2 (en) 2006-09-12 2010-09-07 Hynix Semiconductor Inc. Method of forming fine pattern of semiconductor device
KR102237713B1 (en) 2014-11-17 2021-04-08 삼성전자주식회사 Method of manufacturing a semiconductor device

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