KR960025773A - Column Address Strobe Signal Latch-Up Prevention Circuit - Google Patents
Column Address Strobe Signal Latch-Up Prevention Circuit Download PDFInfo
- Publication number
- KR960025773A KR960025773A KR1019940040587A KR19940040587A KR960025773A KR 960025773 A KR960025773 A KR 960025773A KR 1019940040587 A KR1019940040587 A KR 1019940040587A KR 19940040587 A KR19940040587 A KR 19940040587A KR 960025773 A KR960025773 A KR 960025773A
- Authority
- KR
- South Korea
- Prior art keywords
- address strobe
- strobe signal
- column address
- signal
- latch
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
Abstract
본 발명의 칼럼 어드레스 스트로브 신호 래치-업 방치회로는 메모리 장치에 사용되어 외부로 부터 파우어가 인가되는 순간에 발생할 수 있는 래치-업 현상을 방지한다. 이를 위하여 상기 래치-업 방지회로는 외부로 부터의 칼럼 어드레스 스트로브 신호를 스위치하는 제어용 스위치수단과, 메모리 장치의 전원 안정화 신호 및 외부로 부터의 로우 어드레스 스트로브 신호를 입력하여 상기 제어용 스위치 수단쪽으로 제어신호를 공급하는 제어신호발생수단을 구비한다.The column address strobe signal latch-up neglect circuit of the present invention is used in a memory device to prevent the latch-up phenomenon that may occur at the moment when the power is applied from the outside. To this end, the latch-up prevention circuit includes a control switch means for switching the column address strobe signal from the outside, a power stabilization signal of the memory device and a row address strobe signal from the outside to input the control signal to the control switch means. It is provided with a control signal generating means for supplying.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명의 실시예에 따른 래치 업 방지회로의 회로도, 제3도는 제2도에 도시된 회로의 입ㆍ출력 파형도.2 is a circuit diagram of a latch-up prevention circuit according to an embodiment of the present invention, and FIG. 3 is an input / output waveform diagram of the circuit shown in FIG.
Claims (8)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940040587A KR0144409B1 (en) | 1994-12-31 | 1994-12-31 | Latch-up thwarting circuit of column address strobe signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940040587A KR0144409B1 (en) | 1994-12-31 | 1994-12-31 | Latch-up thwarting circuit of column address strobe signal |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960025773A true KR960025773A (en) | 1996-07-20 |
KR0144409B1 KR0144409B1 (en) | 1998-08-17 |
Family
ID=19406223
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940040587A KR0144409B1 (en) | 1994-12-31 | 1994-12-31 | Latch-up thwarting circuit of column address strobe signal |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0144409B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100480553B1 (en) * | 1997-05-20 | 2005-07-12 | 삼성전자주식회사 | Refresh control method of DRAM device |
-
1994
- 1994-12-31 KR KR1019940040587A patent/KR0144409B1/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100480553B1 (en) * | 1997-05-20 | 2005-07-12 | 삼성전자주식회사 | Refresh control method of DRAM device |
Also Published As
Publication number | Publication date |
---|---|
KR0144409B1 (en) | 1998-08-17 |
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