KR960025773A - Column Address Strobe Signal Latch-Up Prevention Circuit - Google Patents

Column Address Strobe Signal Latch-Up Prevention Circuit Download PDF

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Publication number
KR960025773A
KR960025773A KR1019940040587A KR19940040587A KR960025773A KR 960025773 A KR960025773 A KR 960025773A KR 1019940040587 A KR1019940040587 A KR 1019940040587A KR 19940040587 A KR19940040587 A KR 19940040587A KR 960025773 A KR960025773 A KR 960025773A
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KR
South Korea
Prior art keywords
address strobe
strobe signal
column address
signal
latch
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Application number
KR1019940040587A
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Korean (ko)
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KR0144409B1 (en
Inventor
김정필
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김주용
현대전자산업 주식회사
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Priority to KR1019940040587A priority Critical patent/KR0144409B1/en
Publication of KR960025773A publication Critical patent/KR960025773A/en
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Publication of KR0144409B1 publication Critical patent/KR0144409B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)

Abstract

본 발명의 칼럼 어드레스 스트로브 신호 래치-업 방치회로는 메모리 장치에 사용되어 외부로 부터 파우어가 인가되는 순간에 발생할 수 있는 래치-업 현상을 방지한다. 이를 위하여 상기 래치-업 방지회로는 외부로 부터의 칼럼 어드레스 스트로브 신호를 스위치하는 제어용 스위치수단과, 메모리 장치의 전원 안정화 신호 및 외부로 부터의 로우 어드레스 스트로브 신호를 입력하여 상기 제어용 스위치 수단쪽으로 제어신호를 공급하는 제어신호발생수단을 구비한다.The column address strobe signal latch-up neglect circuit of the present invention is used in a memory device to prevent the latch-up phenomenon that may occur at the moment when the power is applied from the outside. To this end, the latch-up prevention circuit includes a control switch means for switching the column address strobe signal from the outside, a power stabilization signal of the memory device and a row address strobe signal from the outside to input the control signal to the control switch means. It is provided with a control signal generating means for supplying.

Description

칼럼 어드레스 스트로브 신호 래치 업 방지회로Column Address Strobe Signal Latch-Up Prevention Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 실시예에 따른 래치 업 방지회로의 회로도, 제3도는 제2도에 도시된 회로의 입ㆍ출력 파형도.2 is a circuit diagram of a latch-up prevention circuit according to an embodiment of the present invention, and FIG. 3 is an input / output waveform diagram of the circuit shown in FIG.

Claims (8)

외부로 부터의 칼럼 어드레스 스트로브 신호를 스위치하는 제1제어용 스위치 수단과, 메모리 장치의 전원안정화 신호 및 외부로 부터의 로우 어드레스 스트로브 신호를 입력하여 상기 제1제어용 스위치 수단쪽으로 제어신호를 공급하는 제어신호발생수단을 구비한 것을 특징으로 하는 칼럼 어드레스 스트로브 신호 래치-업 방지회로.A first control switch means for switching the column address strobe signal from the outside, a control signal for supplying a control signal to the first control switch means by inputting a power stabilization signal of the memory device and a row address strobe signal from the outside; A column address strobe signal latch-up prevention circuit, comprising: a generating means. 제1항에 있어서, 상기 제어신호발생수단이, 로우 어드레스 스트로브 신호가 인액티브되는 에지를 검출하는 에지검출수단과, 상기 에지검출수단으로 부터의 신호 및 반도체 메모리 장치의 전원 안정화 신호를 논리조합하는 제1논리조합수단을 구비한 것을 특징으로 하는 칼럼 어드레스 스트로브 신호 래치-업 방지회로.The semiconductor memory device according to claim 1, wherein said control signal generating means logically combines edge detection means for detecting an edge at which a row address strobe signal is inactive, a signal from said edge detection means, and a power stabilization signal of a semiconductor memory device. And a first logical combining means. 제2항에 있어서, 상기 에지검출수단이, 상기 로우 어드레스 스트로브 신호를 지연시키는 지연라인과, 상기 에지검출수단으로 부터의 신호 및 상기 지연라인으로 부터의 신호를 논리조합하는 제2논리조합수단을 구비한 것을 특징으로 하는 칼럼 어드레스 스트로브 신호 래치-업 방지회로.3. The second logical combining means according to claim 2, wherein said edge detecting means comprises: a delay line for delaying said row address strobe signal, and a second logical combining means for logically combining a signal from said edge detection means and a signal from said delay line. And a column address strobe signal latch-up preventing circuit. 제3항에 있어서, 상기 논리조합수단의 출력에 의하여 상기 로우 어드레스 스트로브 신호를 상기 지연라인및 제2논리조합수단 쪽으로 전송하는 제2제어용 스위치수단을 추가로 구비한 것을 특징으로 하는 칼럼 어드레스 스트로브신호 래치-업 방지회로.4. The column address strobe signal according to claim 3, further comprising a second control switch means for transmitting the row address strobe signal to the delay line and the second logical combining means by an output of the logical combining means. Latch-up prevention circuit. 제4항에 있어서, 상기 제2제어용 스위치수단이 NOR게이트를 포함하는 것을 특징으로 하는 칼럼 어드레스스트로브 신호 래치-업 방지회로.5. The column address strobe signal latch-up prevention circuit according to claim 4, wherein said second control switch means comprises a NOR gate. 제3항에 있어서, 상기 제2논리조합수단이 NOR게이트를 포함하는 것을 특징으로 하는 칼럼 어드레스 스트로브 신호 래치-업 방지회로.4. The column address strobe signal latch-up preventing circuit according to claim 3, wherein said second logical combining means comprises a NOR gate. 제2항에 있어서, 상기 제1논리조합수단이 NAND게이트를 포함하는 것을 특징으로 하는 칼럼 어드레스 스트로브 신호 래치-업 방지회로.3. The column address strobe signal latch-up prevention circuit according to claim 2, wherein said first logical combining means comprises a NAND gate. 제1항에 있어서, 상기 제1제어용 스위치수단이 NAND게이트를 포함하는 것을 특징으로 하는 칼럼 어드레스 스트로브 신호 래치-업 방지회로.2. The column address strobe signal latch-up prevention circuit according to claim 1, wherein said first control switch means includes a NAND gate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940040587A 1994-12-31 1994-12-31 Latch-up thwarting circuit of column address strobe signal KR0144409B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940040587A KR0144409B1 (en) 1994-12-31 1994-12-31 Latch-up thwarting circuit of column address strobe signal

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Application Number Priority Date Filing Date Title
KR1019940040587A KR0144409B1 (en) 1994-12-31 1994-12-31 Latch-up thwarting circuit of column address strobe signal

Publications (2)

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KR960025773A true KR960025773A (en) 1996-07-20
KR0144409B1 KR0144409B1 (en) 1998-08-17

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100480553B1 (en) * 1997-05-20 2005-07-12 삼성전자주식회사 Refresh control method of DRAM device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100480553B1 (en) * 1997-05-20 2005-07-12 삼성전자주식회사 Refresh control method of DRAM device

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