KR960002558A - Via hole formation method of semiconductor device - Google Patents

Via hole formation method of semiconductor device Download PDF

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Publication number
KR960002558A
KR960002558A KR1019940013896A KR19940013896A KR960002558A KR 960002558 A KR960002558 A KR 960002558A KR 1019940013896 A KR1019940013896 A KR 1019940013896A KR 19940013896 A KR19940013896 A KR 19940013896A KR 960002558 A KR960002558 A KR 960002558A
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KR
South Korea
Prior art keywords
via hole
film
imo
semiconductor device
forming
Prior art date
Application number
KR1019940013896A
Other languages
Korean (ko)
Inventor
오세준
홍상기
손기근
고재완
구영모
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940013896A priority Critical patent/KR960002558A/en
Publication of KR960002558A publication Critical patent/KR960002558A/en

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Abstract

본 발명은 반도체소자의 비아홀(via hole) 형성방법에 관한 것으로, 소자간 절연 및 표면 평탄화를 목적으로 IMO-SOG-IMO의 적층구조를 갖는 층간 절연막을 비아홀 마스크로 식각하여 비아홀을 형성할 때 비아홀 측벽에 도출되는 SOG막으로 인한 소자 결합을 방지하기 위하여, IMO막 및 SOG막을 순차적으로 형성한 후 비아홀 마스크의 홀 크기보다 큰 마스크를 사용하여 하부의 IMO막이 드러날 정도로 SOG막을 식각하고, 이후 전체구조 상부에 IMO막을 형성한 후 비아홀 마스크를 사용하여 하부의 금속층과 연통되는 비아홀을 형성하므로써, 형성된 비아홀 측벽에 SOG막이 노출되지 않아 소자의 수율과 신뢰성을 향상시킬 수 있는 반도체 소자의 비아홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a via hole in a semiconductor device, wherein the via hole is formed by etching an interlayer insulating film having an IMO-SOG-IMO layer structure with a via hole mask for the purpose of insulating and surface planarization between devices. In order to prevent device coupling due to the SOG film derived from the sidewall, the IMO film and the SOG film are sequentially formed, and then the SOG film is etched to the extent that the lower IMO film is exposed by using a mask larger than the hole size of the via hole mask, and then the entire structure. A method of forming a via hole of a semiconductor device in which an SOG film is not exposed on a sidewall of a formed via hole by using an via hole mask after forming an IMO film thereon, thereby improving the yield and reliability of the device. will be.

Description

반도체소자의 비아 홀 형성방법Via hole formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1A도 내지 제1E도는 본 발명에 의한 비아홀 형성방법을 설명하기 위한 소자의 단면도.1A to 1E are cross-sectional views of elements for explaining the method for forming via holes according to the present invention.

Claims (2)

SOG막이 포함된 적층구조를 갖는 층간 절연막에 금속배선간을 연결시키기 위한 반도체 소자의 비아홀 형성방법에 있어서, 하부 금속배선(3)을 포함한 전체구조 상부에 제1 IMO막(5) 및 SOG막(6)을 순차적으로 적층한 후 소정의 마스크를 이용한 식각공정으로 상기 제1 IMO막(5)이 충분히 드러나도록 상기 SOG막(6)을 식각하여 비아홀이 형성될 부분에 홈(8)을 형성하는 단계와, 상기 단계로부터 전체구조 상부에 제2 IMO막(9)을 형성한 후 비아홀 마스크를 이용한 식각공정으로 제2 및 1 IMO막(9 및 5)을 식각하여 하부 금속배선(3)이 드러나는 비아홀(11)을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체소자의 비아홀 형성방법.In the via-hole forming method of a semiconductor device for connecting between metal wirings to an interlayer insulating film having a stacked structure including a SOG film, the first IMO film 5 and the SOG film (on the entire structure including the lower metal wiring 3) 6) are sequentially stacked, and the SOG film 6 is etched so that the first IMO film 5 is sufficiently exposed by an etching process using a predetermined mask to form grooves 8 in portions where via holes are to be formed. And forming the second IMO film 9 on the entire structure from the step, and etching the second and first IMO films 9 and 5 by an etching process using a via hole mask to expose the lower metal wiring 3. A via hole forming method of a semiconductor device, characterized in that it comprises the step of forming the via hole (11). 제1항에 있어서, 상기 비아홀(11)은 그 직격이 상기 홈(8)의 직경보다 작게 형성되는 것을 특징으로 하는 반도체소자의 비아홀 형성방법.2. The method of claim 1, wherein the via hole (11) is formed to have a direct line smaller than the diameter of the groove (8). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940013896A 1994-06-20 1994-06-20 Via hole formation method of semiconductor device KR960002558A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940013896A KR960002558A (en) 1994-06-20 1994-06-20 Via hole formation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940013896A KR960002558A (en) 1994-06-20 1994-06-20 Via hole formation method of semiconductor device

Publications (1)

Publication Number Publication Date
KR960002558A true KR960002558A (en) 1996-01-26

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940013896A KR960002558A (en) 1994-06-20 1994-06-20 Via hole formation method of semiconductor device

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KR (1) KR960002558A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100252533B1 (en) * 1996-12-30 2000-05-01 김영환 Process for forming metal interconnector of semiconductor device
KR100415988B1 (en) * 2001-04-16 2004-01-24 아남반도체 주식회사 Method for forming a via hole

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100252533B1 (en) * 1996-12-30 2000-05-01 김영환 Process for forming metal interconnector of semiconductor device
KR100415988B1 (en) * 2001-04-16 2004-01-24 아남반도체 주식회사 Method for forming a via hole

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