KR960002558A - Via hole formation method of semiconductor device - Google Patents
Via hole formation method of semiconductor device Download PDFInfo
- Publication number
- KR960002558A KR960002558A KR1019940013896A KR19940013896A KR960002558A KR 960002558 A KR960002558 A KR 960002558A KR 1019940013896 A KR1019940013896 A KR 1019940013896A KR 19940013896 A KR19940013896 A KR 19940013896A KR 960002558 A KR960002558 A KR 960002558A
- Authority
- KR
- South Korea
- Prior art keywords
- via hole
- film
- imo
- semiconductor device
- forming
- Prior art date
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 비아홀(via hole) 형성방법에 관한 것으로, 소자간 절연 및 표면 평탄화를 목적으로 IMO-SOG-IMO의 적층구조를 갖는 층간 절연막을 비아홀 마스크로 식각하여 비아홀을 형성할 때 비아홀 측벽에 도출되는 SOG막으로 인한 소자 결합을 방지하기 위하여, IMO막 및 SOG막을 순차적으로 형성한 후 비아홀 마스크의 홀 크기보다 큰 마스크를 사용하여 하부의 IMO막이 드러날 정도로 SOG막을 식각하고, 이후 전체구조 상부에 IMO막을 형성한 후 비아홀 마스크를 사용하여 하부의 금속층과 연통되는 비아홀을 형성하므로써, 형성된 비아홀 측벽에 SOG막이 노출되지 않아 소자의 수율과 신뢰성을 향상시킬 수 있는 반도체 소자의 비아홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a via hole in a semiconductor device, wherein the via hole is formed by etching an interlayer insulating film having an IMO-SOG-IMO layer structure with a via hole mask for the purpose of insulating and surface planarization between devices. In order to prevent device coupling due to the SOG film derived from the sidewall, the IMO film and the SOG film are sequentially formed, and then the SOG film is etched to the extent that the lower IMO film is exposed by using a mask larger than the hole size of the via hole mask, and then the entire structure. A method of forming a via hole of a semiconductor device in which an SOG film is not exposed on a sidewall of a formed via hole by using an via hole mask after forming an IMO film thereon, thereby improving the yield and reliability of the device. will be.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제1A도 내지 제1E도는 본 발명에 의한 비아홀 형성방법을 설명하기 위한 소자의 단면도.1A to 1E are cross-sectional views of elements for explaining the method for forming via holes according to the present invention.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940013896A KR960002558A (en) | 1994-06-20 | 1994-06-20 | Via hole formation method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940013896A KR960002558A (en) | 1994-06-20 | 1994-06-20 | Via hole formation method of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR960002558A true KR960002558A (en) | 1996-01-26 |
Family
ID=66685930
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940013896A KR960002558A (en) | 1994-06-20 | 1994-06-20 | Via hole formation method of semiconductor device |
Country Status (1)
Country | Link |
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KR (1) | KR960002558A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100252533B1 (en) * | 1996-12-30 | 2000-05-01 | 김영환 | Process for forming metal interconnector of semiconductor device |
KR100415988B1 (en) * | 2001-04-16 | 2004-01-24 | 아남반도체 주식회사 | Method for forming a via hole |
-
1994
- 1994-06-20 KR KR1019940013896A patent/KR960002558A/en not_active Application Discontinuation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100252533B1 (en) * | 1996-12-30 | 2000-05-01 | 김영환 | Process for forming metal interconnector of semiconductor device |
KR100415988B1 (en) * | 2001-04-16 | 2004-01-24 | 아남반도체 주식회사 | Method for forming a via hole |
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