KR950035543A - 지지판을 보유한 장치 및 부동상태의 겔을 도포하기 위한 방법 - Google Patents

지지판을 보유한 장치 및 부동상태의 겔을 도포하기 위한 방법 Download PDF

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Publication number
KR950035543A
KR950035543A KR1019950003302A KR19950003302A KR950035543A KR 950035543 A KR950035543 A KR 950035543A KR 1019950003302 A KR1019950003302 A KR 1019950003302A KR 19950003302 A KR19950003302 A KR 19950003302A KR 950035543 A KR950035543 A KR 950035543A
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South Korea
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gel
frame
component
floating
support plate
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KR1019950003302A
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English (en)
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바이블렌 쿠르트
보에스너 베르트람
Original Assignee
클라우스 포스.위르겐 프리드만
로베르트 보쉬 게엠베하
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Publication of KR950035543A publication Critical patent/KR950035543A/ko

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/23—Sheet including cover or casing
    • Y10T428/239—Complete cover or casing

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dispersion Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Securing Of Glass Panes Or The Like (AREA)
  • Application Of Or Painting With Fluid Materials (AREA)
  • Laminated Bodies (AREA)

Abstract

본 발명의 목적은 구성소자를 간단하게, 싼 가격으로 하는것 밖에도 신속하게 불활성화 함에 있으며, 구성소자를 불활성화하기 위한 장치 및 방법에 관하여, 이 경우, 틱소트로펜 겔이 링형상으로 구성소자의 주위에 배치되어 있고 틱스트로펜 겔에 의해 둘러싸여진 내측 공간이, 부동 상태의 겔에 의해 구성소자를 완전히 뒤덮기까지, 부동 상태의 겔에 의해 충전되어 있으며, 계속해서 겔이 경화된다.

Description

지지판을 보유한 장치 및 부동상태의 겔을 도포하기 위한 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 틱소트로펜 겔로된 흐름 차단 부재를 도시한 도면, 제2도는 흐름 차단 부재의 횡단면도, 제3도는 프레임과 틱소트로펜 겔로된 흐름 차단 부재를 도시한 도면, 제4도는 방호층의 단면도.

Claims (5)

  1. 구성소자(2)가 배치된 지지판(1)을 보유한 장치에 있어서, 구성소자(2)가 방호층으로서의 부동 상태의 겔(6)에 의해서 덮여져 있으며, 상기 부동 상태의 겔(6)이 측방에서 흐름차단 부재에 의해서 제한되고 있는 형식의 것으로서, 흐름 차단 부재가 틱소트로펜 겔(Thixotropen Gel)을 가지고 있는 것을 특징으로 하는 지지판을 보유한 장치.
  2. 제1항에 있어서, 흐름 차단 부재가 프레임(frame)(9)를 보유하고 있고, 프레임(9)과 지지판(1)과의 사이 또는 프레임(9)과 구성소자(2)와의 사이에 시일(seal)부재로서 틱소트로펜 겔(Thixotropen Gel)이 배치되어 있는 것을 특징으로 하는 지지판을 보유한 장치.
  3. 제2항에 있어서, 프레임(9)이 지지판(1)에 점형태의 접착층(7)을 통해서 고정되어 있는 것을 특징으로 하는 지지판을 보유한 장치.
  4. 지지판(1)에 배치되며 프레임(9)에 의해서 둘러쌓여진 구성소자(2)에, 부동 상태의 겔(6)을 도포하기 위한 방법에 있어서, 프레임(9)를 접착층(7)을 통해서 지지판(9)에 고정하고, 부동 상태의 겔(6)을 프레임(9)의 내측에서 구성소자(2)상으로 주입하고, 계속하여 부동 상태의 겔(6)을 경화시킨 형식의 것으로서, 프레임(9)을 작은 범위에서만 접착층(7)을 통해서 지지판(9)에 고정에 고정하여, 프레임(9)과 지지판(1)에 의해서 형성된 코너(corner)범위에, 틱소트로펜 겔(5)을 충전하고, 계속하여 부동 상태의 겔(6)을 프레임(9)의 내측에서 구성소자(2)상으로 주입하며 이어서 부동 상태의 겔(6) 및 틱소트로펜 겔(5)을 경화시킨 것을 특징으로 하는 부동 상태의 겔(6)을 도포하기 위한 방법.
  5. 제4항에 있어서, 프레임(9)을 부분적으로 다른 구성소자(3)상으로 배치하고, 프레임(9)과 다른 구성소자(3)와의 사이의 코너 범위를 틱소트로펜 겔(5)에 의해서 충전하는 것을 특징으로 하는 부동 상태의 겔(6)을 도포하기 위한 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950003302A 1994-02-23 1995-02-21 지지판을 보유한 장치 및 부동상태의 겔을 도포하기 위한 방법 KR950035543A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4405710A DE4405710A1 (de) 1994-02-23 1994-02-23 Vorrichtung mit einer Trägerplatte und Verfahren zum Aufbringen eines Passivierungsgels
DEP4405710.5 1994-02-23

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Publication Number Publication Date
KR950035543A true KR950035543A (ko) 1995-12-30

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KR1019950003302A KR950035543A (ko) 1994-02-23 1995-02-21 지지판을 보유한 장치 및 부동상태의 겔을 도포하기 위한 방법

Country Status (5)

Country Link
US (1) US5547730A (ko)
JP (1) JPH07263847A (ko)
KR (1) KR950035543A (ko)
CN (1) CN1113070A (ko)
DE (1) DE4405710A1 (ko)

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JP5197175B2 (ja) * 2008-06-16 2013-05-15 キヤノン株式会社 インクジェット記録ヘッドおよびその製造方法
DE102008040676A1 (de) 2008-07-24 2010-01-28 Robert Bosch Gmbh Abdichtrahmen sowie Verfahren zum Abdecken eines Bauteils
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Also Published As

Publication number Publication date
CN1113070A (zh) 1995-12-06
US5547730A (en) 1996-08-20
JPH07263847A (ja) 1995-10-13
DE4405710A1 (de) 1995-08-24

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