KR950034732A - Mask ROM Manufacturing Method - Google Patents

Mask ROM Manufacturing Method Download PDF

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Publication number
KR950034732A
KR950034732A KR1019940010498A KR19940010498A KR950034732A KR 950034732 A KR950034732 A KR 950034732A KR 1019940010498 A KR1019940010498 A KR 1019940010498A KR 19940010498 A KR19940010498 A KR 19940010498A KR 950034732 A KR950034732 A KR 950034732A
Authority
KR
South Korea
Prior art keywords
gate
mask rom
oxide film
transistor
gate electrode
Prior art date
Application number
KR1019940010498A
Other languages
Korean (ko)
Other versions
KR0140645B1 (en
Inventor
김남용
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019940010498A priority Critical patent/KR0140645B1/en
Publication of KR950034732A publication Critical patent/KR950034732A/en
Application granted granted Critical
Publication of KR0140645B1 publication Critical patent/KR0140645B1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38—Doping programmed, e.g. mask ROM
    • H10B20/387—Source region or drain region doping programmed

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  • Semiconductor Memories (AREA)

Abstract

본 발명은 마스크롬 제조방법에 관한 것으로, 한번의 이온주입으로 마스크롬의 커스템에 따른 코딩을 하기 위한 것이다.The present invention relates to a method for manufacturing a mask rom, to perform coding according to the custom of the mask rom with a single ion implantation.

본 발명은 P형 기판에 게이트 산화막과 게이트용 폴리실리콘을 차례로 형성하는 공정과, 상기 게이트용 폴리실리콘과 게이트 산화막을 패터닝하여 디플리션 및 인헨스먼트형 트랜지스터의 게이트전극을 형성하는 공정과, 상기 인헨스먼트형 트랜지스터의 게이트전극만을 감싸도록 선택적으로 마스킹하고 코드불순물을 주입한 다음 어닐링하는 공정을 포함하여 이루어지는 것을 특징으로 이루어진다.The present invention provides a process for forming a gate oxide film and a gate polysilicon on a P-type substrate in sequence, patterning the gate polysilicon and the gate oxide film to form a gate electrode of a depletion and enhancement transistor; And selectively annealing to cover only the gate electrode of the enhancement transistor, injecting a code impurity, and then annealing.

Description

마스크롬 제조방법Mask ROM Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 마스크롬 제조방법을 도시한 공정순서도.2 is a process flowchart showing a method for manufacturing a mask rom of the present invention.

Claims (3)

P형 기판에 게이트 산화막과 게이트용 폴리실리콘을 차례로 형성하는 공정과, 상기 게이트용 폴리실리콘과 게이트 산화막을 패터닝하여 디플리션 및 인헨스먼트형 트랜지스터의 게이트전극을 형성하는 공정과, 상기 인헨스먼트형 트랜지스터의 게이트전극만을 감싸도록 선택적으로 마스킹하고 코드불순물을 주입한 다음 어닐링하는 공정을 포함하여 이루어진 것을 특징으로 하는 마스크롬 제조방법.Forming a gate oxide film and a gate polysilicon sequentially on a P-type substrate; patterning the gate polysilicon and the gate oxide film to form a gate electrode of a depletion and enhancement transistor; and the enhancement And masking only the gate electrode of the transistor, and injecting a code impurity, followed by annealing. 제1항에 있어서, 코드불순물 이온주입은 As+이온을 주입함을 특징으로 하는 마스크롬 제조방법.2. The method of claim 1, wherein the code impurity ion implantation is implanted with As + ions. 제1항에 있어서, 어닐링 공정은 디플리션형 트랜지스터의 소오스 및 드레인 영역에서 사이드 디퓨전되도록 함을 특징으로 하는 마스크롬 제조방법.The method of claim 1, wherein the annealing process causes side diffusion in the source and drain regions of the depletion transistor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940010498A 1994-05-13 1994-05-13 Manufacturing method of mask rom KR0140645B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940010498A KR0140645B1 (en) 1994-05-13 1994-05-13 Manufacturing method of mask rom

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940010498A KR0140645B1 (en) 1994-05-13 1994-05-13 Manufacturing method of mask rom

Publications (2)

Publication Number Publication Date
KR950034732A true KR950034732A (en) 1995-12-28
KR0140645B1 KR0140645B1 (en) 1998-06-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940010498A KR0140645B1 (en) 1994-05-13 1994-05-13 Manufacturing method of mask rom

Country Status (1)

Country Link
KR (1) KR0140645B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3465897B2 (en) * 2001-06-12 2003-11-10 Ｎｅｃマイクロシステム株式会社 Mask ROM

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Publication number Publication date
KR0140645B1 (en) 1998-06-01

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