KR950009980A - Source / Drain region formation method of semiconductor device - Google Patents

Source / Drain region formation method of semiconductor device Download PDF

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Publication number
KR950009980A
KR950009980A KR1019930018758A KR930018758A KR950009980A KR 950009980 A KR950009980 A KR 950009980A KR 1019930018758 A KR1019930018758 A KR 1019930018758A KR 930018758 A KR930018758 A KR 930018758A KR 950009980 A KR950009980 A KR 950009980A
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KR
South Korea
Prior art keywords
source
drain region
semiconductor device
formation method
region formation
Prior art date
Application number
KR1019930018758A
Other languages
Korean (ko)
Inventor
권명연
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930018758A priority Critical patent/KR950009980A/en
Publication of KR950009980A publication Critical patent/KR950009980A/en

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Abstract

본 발명의 반도체 소자의 소오스/드레인 영역 형성방법에 관한 것으로, 반도체 소자의 소오스/드레인 영역 형성시 소오스/드레인 영역이 형성되는 부분만 마스크를 사용하여 개방한 상태에서 불순물 이온주입 공정을 통해 소오스/드레인 영역을 형성하므로써 게이트 영역이 비정질화(Amorphorization)되는 것을 방지할 수 있도록한 반도체 소자의 소오스/드레인 영역 형성방법에 관해 기술된다.The present invention relates to a method for forming a source / drain region of a semiconductor device, wherein the source / drain region is formed only when a source / drain region is formed by using an impurity ion implantation process in a state in which the source / drain region is formed using a mask. A method of forming a source / drain region of a semiconductor device in which a gate region is prevented from being amorphous by forming a drain region is described.

Description

반도체 소자의 소오스/드레인 영역 형성방법Source / Drain region formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1a 내지 제1c도는 본 발명에 따라 반도체 소오스/드레인 영역이 형성되는 단계를 나타내는 단면도.1A-1C are cross-sectional views illustrating steps in forming semiconductor source / drain regions in accordance with the present invention.

Claims (1)

반도체 소자의 소오스/드레인 영역 형성방법에 있어서, 실리콘 기판(1) 상부에 필드 산화막 및 게이트 산화막(2 및 3)을 형성한 상태에서, 게이트 전극용 폴리실리콘 및 스텐 실리사이드(4 및 5)를 증착하고 스페이서 산화막(6)을 형성한 수 전체구조 상부에 포토레지스트(7)를 도포하는 단계와, 상기 단계로부터 상기 실리콘 기판(1)상에 소오스/드레인 영역이 형성될 부분 상부의 상기 포토레지스트(7)를 현상 공정을 통해 패턴화하여 개방하고 불순물 이온 주입공정을 실시하여 소오스/드레인 영역(8)을 형성한 후 상기 포토레지스트(7)를 제거하는 단계로 이루어진 것을 특징으로 하는 반도체 소자의 소오스/드레인 영역 형성방법.In the method of forming a source / drain region of a semiconductor device, polysilicon and stainless silicides 4 and 5 for gate electrodes are deposited while the field oxide film and the gate oxide films 2 and 3 are formed on the silicon substrate 1. And applying a photoresist 7 over the whole structure having the spacer oxide film 6 formed thereon, and from the step the photoresist above the portion where the source / drain regions are to be formed on the silicon substrate 1. 7) patterning and opening the wafer through a development process, and performing a source of impurity ion implantation to form a source / drain region 8, and then removing the photoresist 7. / Drain region formation method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930018758A 1993-09-17 1993-09-17 Source / Drain region formation method of semiconductor device KR950009980A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930018758A KR950009980A (en) 1993-09-17 1993-09-17 Source / Drain region formation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930018758A KR950009980A (en) 1993-09-17 1993-09-17 Source / Drain region formation method of semiconductor device

Publications (1)

Publication Number Publication Date
KR950009980A true KR950009980A (en) 1995-04-26

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930018758A KR950009980A (en) 1993-09-17 1993-09-17 Source / Drain region formation method of semiconductor device

Country Status (1)

Country Link
KR (1) KR950009980A (en)

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