KR950006613A - Bus transfer between central processing unit and peripherals - Google Patents

Bus transfer between central processing unit and peripherals Download PDF

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Publication number
KR950006613A
KR950006613A KR1019940017013A KR19940017013A KR950006613A KR 950006613 A KR950006613 A KR 950006613A KR 1019940017013 A KR1019940017013 A KR 1019940017013A KR 19940017013 A KR19940017013 A KR 19940017013A KR 950006613 A KR950006613 A KR 950006613A
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KR
South Korea
Prior art keywords
signal
output
bus
gate
bus permission
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KR1019940017013A
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Korean (ko)
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KR960016406B1 (en
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임재관
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장정호
금성정보통신 주식회사
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling
    • G06F13/225—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

본 발명은 계열이 다른 소자로 구성된 회로에서도 주변장치가 버스관할자(Bus master)가 될 수 있도록함과 아울러 CPU가 이미 명령수형중일때도 적절한 버스 이용권을 콘크롤 하도록 한 CPU와 주변장치간의 버스이양장치에 관한 것이다.The present invention enables a peripheral device to become a bus master even in a circuit composed of different devices, and also transfers a bus between a CPU and a peripheral device so that the CPU can control an appropriate bus pass even when the CPU is already in command form. Relates to a device.

이러한 본 고안은 각각의 주변장치에서 출력된 버스요구신호 및 중앙처리장치에서 출력된 버스허가신호, 어드레스 스트로브신호 및 클럭펄스에 버스허가신호를 발생하는 다수개의 버스허가 신호 발생기를 포함하는 버스허가 신호 발생수단과, 상기 버스허가신호 발생수 단내의 다수개의 버스허가 신호 발생기로부터 각각 발생된 버스허가신호를 우선순위에 따라 처리하여 버스허가신호를 출력하는 버스허가신호처리수단과, 상기 버스허가신호처리수단에서 출력된 버스허가신호에 따라 버스허가인식신호를 발생하는 다수개의 버스허가인식신호발생기를 포함하는 버스허가인식신호 발생수단으로 구성된다.The present invention has a bus permission signal including a bus request signal output from each peripheral device and a bus permission signal output from the central processing unit, a bus permission signal generator for generating an address permission signal and a clock permission signal from a clock pulse. Bus permission signal processing means for processing a bus permission signal generated from a plurality of bus permission signal generators within the bus permission signal generation means according to priority and outputting a bus permission signal; and the bus permission signal processing And a bus permission recognition signal generating means including a plurality of bus permission recognition signal generators for generating a bus permission recognition signal in accordance with the bus permission signal output from the means.

Description

중앙처리장치와 주변장치간의 버스이양장치Bus transfer between central processing unit and peripherals

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명 중앙처리장치와 주변장치간의 버스이양장치 구성도,2 is a block diagram of a bus transfer device between the present invention and the central processing unit;

제3도는 제2도의 버스허가신호 발생부 제1실시예도,FIG. 3 is a first embodiment of the bus permission signal generator of FIG.

제4도는 제2도의 버스허가 신호 발생부 제2실시예도.4 is a second embodiment of the bus permission signal generator of FIG.

Claims (3)

각각의 주변장치에 출력된 버스요구신호 및 중앙처리장치에서 출력된 버스허가신호, 어드레스 스트로브신호 및 클럭펄스에 따라 버스허가신호를 발생하는 다수개의 버스허가 신호 발생기를 포함하는 버스허가신호 발생 수단과, 상기 버스허가신호를 발생수단내의 다수개의 버스허가 신호 발생기로부터 각각 발생된 버스허가신호를 우선순위에 따라 처리하여 버스허가신호를 출력하는 버스허가신호 처리수단과, 상기 버스허가신호 처리수단에서 출력된 버스허가신호에 따라 버스허가인식신호를 발생하는 다수개의 버스허가인식신호 발생기를 포함하는 버스 허가인식신호 발생수단으로 구성됨을 특징으로 한 중앙처리장치와 주변장치간의 버스이양장치.Bus permission signal generating means including a bus request signal output to each peripheral device and a bus permission signal output from the central processing unit, and a bus permission signal generator for generating a bus permission signal according to an address strobe signal and a clock pulse; Bus permission signal processing means for processing a bus permission signal generated from a plurality of bus permission signal generators in the means for generating a bus permission signal according to priority, and outputting from the bus permission signal processing means; And a bus permission recognition signal generating means comprising a plurality of bus permission recognition signal generators for generating a bus permission recognition signal in accordance with a predetermined bus permission signal. 제1항에 있어서, 상기 버스허가신호 발생수단은 하나의 버스허가신호 발생기가 상기 중앙처리장치에서 출력된 버스허가신호를 위상반전시키는 제1인버터와, 상기 제1인버터에서 출력된 신호와 상기 중앙처리장치에서 출력된 어드레스 스트로브신호를 부정논리곱사는 제1낸드게이트와, 상기 제1낸드게이트의 출력과 주변장치에서 출력된 버스요구신호를 논리합하는 오아게이트와, 상기 주변장치로 출력되는 버스허가신호를 위상반전시키는 제2인버터와, 상기 제2인버터게이트의 출력신호와 상기 제1낸드게이트의 출력값을 부정논리 곱하는 제2낸드게이트와, 상기 제2낸드게이트의 출력과 상기오아게이트의 출력을 부정논리 곱하는데 제3낸드게이트와, 외부에서 입력된 글로펄스에 따라 상기 제3낸드게이트의 출력을 소정시간 지연시켜 버스허가 신호로 출력하는 D플립플롭으로 구성된 것을 특징으로 하는 중앙처리장치와 주변장치간의 버스이양장치.2. The apparatus of claim 1, wherein the bus permission signal generating means comprises: a first inverter in which one bus permission signal generator phase-inverts a bus permission signal output from the central processing unit, a signal output from the first inverter, and the center; The negative logic multiply of the address strobe signal output from the processing device is an OR gate which logically combines a first NAND gate, an output of the first NAND gate and a bus request signal output from a peripheral device, and a bus permission output to the peripheral device. A second inverter for inverting the phase of the signal, a second NAND gate that negatively multiplies the output signal of the second inverter gate with the output value of the first NAND gate, an output of the second NAND gate, and an output of the oA gate. In order to multiply a negative logic, a bus permit signal is generated by delaying a third NAND gate and an output of the third NAND gate for a predetermined time according to an externally input glow pulse. Bus transfer device between the central processing unit and the peripheral device, characterized in that consisting of the D flip-flop to output. 제1항에 있어서, 상기 버스허가 신호 발생수단은 하나의 버스허가신호 발생기가 상기 중앙처리장치에서 발생된 어드레스 스트로브 신호와, 제1인버터 게이트에 위상 전반된 버스허가신호와를 논리곱하는게 제1앤드게이트와, 상기 주변장치로부터 발생된 버스요구신호와 제2인버터게이트에 의해 위상 반전된 상기 제1앤드게이트의 출력신호와를 논리합하는 오아게이트와 상기 제2인버터게이트의 출력신호와, D플립플롭의 출력신호와는 논리곱하는 제2앤드게이트와, 상기 오아게이트의 출력신호와 제3인버터 게이트를 통해 위상반전된 상기 제2앤드게이트의 출력신호와를 논리곱하는 제3앤드게이트와 상기 중앙처리장치에서 출력된 클럭펄스가 상승에지일 때, 제4인버터 게이트를 통해 위상반전된 상기 제3앤드게이트의 출력신호를 출력값으로 출력하는 D플립플롭과, 상기 중앙처리장치로부터 발생된 제1 내지 제3가능신호를 논리곱하는 제4앤드게이트와, 상기 D플립플롭의 출력신호와 제5인버터 게이트를 통한 상기 제4앤드게이트의 출력신호와를 논리곱하는 제5앤드게이트와, 상기 제5앤드게이트의 출력신호를 위상반전시켜 버스허가신호를 출력하는 제6인버터 게이트로 구성된 것을 특징으로 하는 중앙처리장치와 주변장치간의 버스이양장치.2. The first bus permission signal generating means according to claim 1, wherein the bus permission signal generator is configured to logically multiply an address strobe signal generated by the CPU and the bus permission signal phase-shifted to the first inverter gate. An OR gate, an OR signal for ORing the bus request signal generated from the peripheral device, and an output signal of the first and gate inverted in phase by the second inverter gate, an output signal of the second inverter gate, and a D flip A second end gate, which is logically multiplied with the output signal of the flop, a third end gate which is logically ANDed by the output signal of the oragate and the output signal of the second and gate phase-inverted through the third inverter gate, and the central processing. When the clock pulse output from the device is rising edge, the output signal of the third and gate phase-inverted through the fourth inverter gate is output as an output value. A fourth flip-off of the D flip-flop, the first to third possible signals generated from the central processing unit, an output signal of the D flip-flop, and an output signal of the fourth end gate through the fifth inverter gate And a fifth inverter gate multiplied by AND, and a sixth inverter gate inverting an output signal of the fifth gate to output a bus permission signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940017013A 1993-08-03 1994-07-14 Bus transferring apparatus between cpu and peripheral KR960016406B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR930015050 1993-08-03
KR93-15050 1993-08-03

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KR950006613A true KR950006613A (en) 1995-03-21
KR960016406B1 KR960016406B1 (en) 1996-12-11

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