KR950006128Y1 - Semiconduct chip pack - Google Patents
Semiconduct chip pack Download PDFInfo
- Publication number
- KR950006128Y1 KR950006128Y1 KR92018029U KR920018029U KR950006128Y1 KR 950006128 Y1 KR950006128 Y1 KR 950006128Y1 KR 92018029 U KR92018029 U KR 92018029U KR 920018029 U KR920018029 U KR 920018029U KR 950006128 Y1 KR950006128 Y1 KR 950006128Y1
- Authority
- KR
- South Korea
- Prior art keywords
- box
- pack
- packaging pack
- semiconductor chip
- paper
- Prior art date
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Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
- B65D—CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
- B65D75/00—Packages comprising articles or materials partially or wholly enclosed in strips, sheets, blanks, tubes, or webs of flexible sheet material, e.g. in folded wrappers
- B65D75/28—Articles or materials wholly enclosed in composite wrappers, i.e. wrappers formed by associating or interconnecting two or more sheets or blanks
- B65D75/30—Articles or materials enclosed between two opposed sheets or blanks having their margins united, e.g. by pressure-sensitive adhesive, crimping, heat-sealing, or welding
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
- B65D—CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
- B65D85/00—Containers, packaging elements or packages, specially adapted for particular articles or materials
- B65D85/30—Containers, packaging elements or packages, specially adapted for particular articles or materials for articles particularly sensitive to damage by shock or pressure
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- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Packaging Frangible Articles (AREA)
Abstract
내용 없음.No content.
Description
제 1 도는 본 고안의 사시도.1 is a perspective view of the present invention.
제 2a 도는 본 고안의 포장팩을 접은 상태의 평면도, (b)는 본 고안의 포장팩을 펼친 상태의 평면도.Figure 2a is a plan view of the folded state of the packaging pack of the present invention, (b) is a plan view of the state unfolding the packaging pack of the present invention.
제 3 도는 제 1 도의 횡단면도.3 is a cross-sectional view of FIG. 1.
제 4 도는 종래 고안의 횡단면도.4 is a cross-sectional view of a conventional design.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10a, 10b, 10c, 10d : 전, 후, 좌, 우면 비닐지10a, 10b, 10c, 10d: front, back, left, right side plastic paper
11 : 측단부 13, 12 : 상, 하단부11: side end 13, 12: top, bottom
20 : 박스20: box
본 고안의 반도체 칩용 포장팩에 관한 것으로서, 특히 반도체 칩이 수장된 박스가 포장팩 내부에서 유돔됨이 없도록 사각형태의 포장팩으로 형성하여 정전기의 발생을 방지 하도록 안출된 반도체 칩용 포장팩에 관한 것이다.The present invention relates to a packaging pack for a semiconductor chip of the present invention, and more particularly, to a packaging pack for a semiconductor chip that is formed to prevent the occurrence of static electricity by forming a rectangular packaging pack so that a box containing the semiconductor chips is free from the inside of the packaging pack. .
종래에는 반도체 칩을 포장하기 위하여 일정한 크기의 비닐지 중앙에 접어 그 단부를 열 융착하여 포장하는 방법이 사용되었고, 또 제 4 도에서와 같이 양면으로 된 비닐지의 단부를 상, 하, 좌, 우로 열 융착하여서된 포장팩이 있었으나, 이와같은 종래의 포장팩은 공정상 정밀한 규격의 제품생산의 불가능 함으로서, 포장팩의 사용시 취급자의 세심한 주의와 노력을 요구케 되는 등의 문제점이 있었던 것이다.Conventionally, in order to package a semiconductor chip, a method of folding the end of a plastic paper of a certain size and heat-sealing the end thereof is used. Also, as shown in FIG. 4, the ends of the double-sided plastic paper are rolled up, down, left, and right. Although there was a heat-sealed packing pack, such a conventional packing pack is impossible to produce a precise specification of the process, there is a problem such as requiring careful attention and effort of the operator when using the packaging pack.
일반적으로 초정밀도를 요구하는 반도체 칩은 습도, 먼지, 온도변화, 외부충격등에 의하여 제품이 지대한 영향을 받게 됨을 이미 주지된 사실이다. 따라서 이같은 악 영향으로부터 반도체 칩을 보호하기 위하여 반도체 칩을 사각체 박스에 수장하고 재차 포장팩으로 포장 하였으나, 상기한 종래의 포장팩은 사각체의 박스 규격에 따른 밀접한 상태로의 포장이 불가능함으로서, 보관및 운반시 포장팩의 내부에서 사각체의 박스가 유동을 하게 되고 이때 마찰에 의해 발생되는 정전기로 인하여 반도체 칩에 악 영향을 주게 되어 제품의 특성을 변하게 하는 단점이 있었던 것이다.In general, semiconductor chips that require ultra-precision are already well known that their products are greatly affected by humidity, dust, temperature changes, and external shocks. Therefore, in order to protect the semiconductor chip from such adverse influences, the semiconductor chip was placed in a rectangular box and again packed in a packing pack, but the conventional packing pack cannot be packed in a close state according to the box specification of the rectangular box, During storage and transport, the box of the rectangular body flows inside the packing pack, and this has a disadvantage in that the characteristics of the product are changed by adversely affecting the semiconductor chip due to static electricity generated by friction.
본 고안의 상기한 종래의 제반 문제점을 개선하고 제품의 신뢰성을 재고하여 다양한 제품을 제공토록 함을 목적으로 고안된 것으로서, 이하 첨부된 도면에 의거하여 상세히 설명하면 다음과 같다.It is designed to provide a variety of products by improving the above-mentioned conventional problems of the present invention and to reconsider the reliability of the product, it will be described in detail based on the accompanying drawings as follows.
본 고안의 포장팩(10)은 제 1 도 내제 제 3 도에서와 같이 4겹의 비닐지 또는 합성수지로서 성형된 전면비닐지 (10a), 후면비닐지(10b), 좌면비닐지(10c), 우면비닐지(10d)로서 구성된다.The packaging pack 10 of the present invention is a front vinyl paper (10a), a rear plastic paper (10b), a seating plastic paper (10c), molded as a four-ply plastic or synthetic resin as shown in Fig. It is comprised as the right side vinyl paper 10d.
먼저 상기 전, 후면비닐지(10a)(10b)와 좌, 우면비닐지(10c)(10d)를 사각체의 박스(20)의 규격이 고려된 크기로 성형하되, 그 전, 후면비닐지(10a)(10b)와 좌, 우면비닐지(10c)(10d)가 만나는 사방의 측단부(11)를 열융착하고 좌, 우면비닐지(10c)(10d)의 중앙을 접은 상태에서 전, 후면비닐지(10a)(10b)와 좌, 우면비닐지(10c)(10d)가 만나는 하단부(12)를 십자형으로 열 융착하여 구성된다. 여기서 상기 포장팩(10)의 상측으로 반도체 칩이 수장된 사각체 박스(20)를 투입하고 상기한 하단부(12)와 같은 방법으로 하여 전, 후면비닐지(10a)(10b)와 좌, 우면비닐지(10c)(10d)가 만나는 상단부(13)를 십자형태로 열융착하여 포장되는 것이다.First, the front and rear vinyl paper (10a) (10b) and the left, right side vinyl paper (10c) (10d) to be molded in the size considering the size of the box 20 of the rectangular body, the front, the rear plastic paper ( 10a, 10b and the left and right side vinyl papers 10c, 10d on each side where the side end portions 11 meet and heat-sealed, and the left and right side vinyl paper 10c, 10d in the state folded back The lower end 12 where the vinyl paper 10a, 10b and the left and right side vinyl paper 10c, 10d meet is thermally fused in a cross shape. Here, the rectangular box 20 in which the semiconductor chip is stored is inserted into the upper side of the packing pack 10, and the front and rear vinyl papers 10a and 10b and the left and right sides are made in the same manner as the lower end 12. The upper end portion 13 where the plastic sheets 10c and 10d meet is packaged by heat-sealing in a cross shape.
이와같이 구성된 본 고안은 제 3 도에서와 같이 포장팩(10)의 사방이 측단부(11)가 열 융착되고, 상, 하단부(13)(12)가 십자 형태로 열 융착되어 반도체가 수장된 사각체의 박스(20)를 밀접한 상태로 진공포장을 하게 됨으로서, 정전기의 발생을 방지케 되는 것이다.The present invention constructed as described above has four sides of the packaging pack 10 as shown in FIG. 3, wherein the side end portions 11 are thermally fused, and the upper and lower ends 13 and 12 are thermally fused in a cross shape, where the semiconductor is enclosed. By vacuum packing the box 20 of the sieve closely, it is to prevent the generation of static electricity.
즉, 포장팩(10)의 전, 후, 좌, 우면의 비닐지(10a)(10b)(10c)(10d)의 크기를 사각체의 박스(20)규격에 따라 성형한 상태에서 전, 후, 좌, 우면비닐지(10a)(10b)(10c)(10d)가 만나는 측단부(11)를 열융착하고 좌, 우면비닐지(10c)(10d)의 중간을 접은 상태에서 전, 후면비닐지(10a)(10b)와 좌, 우면비닐지(10c)(10d)가 만나는 하단부(12)를 십자형태로 열 융착 함으로서, 사각체의 박스(20) 규격에 맞는 정밀한 사각형태의 포장팩(10)을 형성게 되는 것이다. 따라서 상기 포장팩(10)의 상측으로 반도체 칩이 수장된 사각체의 박스(20)를 투입하고 상단부(13)를 십자형태로 열 융착하여 포장하게 되어 포장팩(10)의 내부에서 사각체의 박스(20)가 밀접하게 포장되는 것이고, 포장팩(10) 내부에서 사각체의 박스(20)의 유동에 의한 정전기 발생을 방지할 수 있게 되는 것이다.In other words, before and after the packaging pack 10, before and after the state of the plastic paper 10a, 10b, 10c, 10d on the left and right sides molded in accordance with the rectangular box 20 standard , Front and rear vinyl in the state where the left and right side vinyl papers 10a, 10b, 10c, 10d meet and heat-bond the side ends 11 and the middle of the left and right side vinyl papers 10c, 10d. By heat-sealing the lower end portion 12 where the paper 10a, 10b and the left and right side vinyl paper 10c, 10d meet in a cross shape, a precise rectangular packaging pack conforming to the box 20 standard of a rectangular box ( 10) will be formed. Accordingly, the box 20 of the rectangular body in which the semiconductor chip is stored is inserted into the upper side of the packaging pack 10, and the upper end 13 is thermally fused in a cross shape to package the rectangular body in the interior of the packaging pack 10. The box 20 is to be closely packed, it is possible to prevent the generation of static electricity due to the flow of the box 20 of the rectangular body in the packaging pack 10.
상기한 바와같이 본 고안은 반도체 칩을 먼지, 습기등의 영향으로 부터 보호할 수 있음은 물론이고, 포장팩(10)의 내부에서 박스(20)가 유동함으로서 발생되는 정전기를 방지하여 제품의 실뢰성을 재고하고 다양한 제품을 제공케 되는 것으로서, 매우 유용한 고안인 것이다.As described above, the present invention not only protects the semiconductor chip from the influence of dust, moisture, etc., but also prevents the static electricity generated by the flow of the box 20 inside the packaging pack 10, thereby preventing the sealing of the product. It is a very useful design to rethink the reliability and provide a variety of products.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR92018029U KR950006128Y1 (en) | 1992-09-22 | 1992-09-22 | Semiconduct chip pack |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR92018029U KR950006128Y1 (en) | 1992-09-22 | 1992-09-22 | Semiconduct chip pack |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940008678U KR940008678U (en) | 1994-04-21 |
KR950006128Y1 true KR950006128Y1 (en) | 1995-07-29 |
Family
ID=19340478
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR92018029U KR950006128Y1 (en) | 1992-09-22 | 1992-09-22 | Semiconduct chip pack |
Country Status (1)
Country | Link |
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KR (1) | KR950006128Y1 (en) |
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1992
- 1992-09-22 KR KR92018029U patent/KR950006128Y1/en not_active IP Right Cessation
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Publication number | Publication date |
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KR940008678U (en) | 1994-04-21 |
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