KR950004033A - How to implement a FIR filter that does not require a multiplier with a programmable power of 2 - Google Patents

How to implement a FIR filter that does not require a multiplier with a programmable power of 2 Download PDF

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KR950004033A
KR950004033A KR1019930014360A KR930014360A KR950004033A KR 950004033 A KR950004033 A KR 950004033A KR 1019930014360 A KR1019930014360 A KR 1019930014360A KR 930014360 A KR930014360 A KR 930014360A KR 950004033 A KR950004033 A KR 950004033A
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South Korea
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shifter
multiplier
fir filter
implement
require
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KR1019930014360A
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Korean (ko)
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KR960014183B1 (en
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이용훈
오우진
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천성순
한국과학기술원
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations

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Abstract

본 발명은 프로그램 가능한 FIR 필터의 구현방법에 관한 것으로서, 복잡한 구조의 쉬프터(shifter)를 개선시키거나 처리속도의 향상을 위해 쉬프터(shifter)의 크기를 줄일 수 있도록 CSD(cannonical signed digit)코드로 표현 가능한 필터의 계수 h(n)이The present invention relates to a method for implementing a programmable FIR filter, which is expressed in canonical signed digit (CSD) code to reduce the size of the shifter for improving the shifter of a complex structure or for improving the processing speed. The coefficient h (n) of the possible filters

이라 할 때, 상기 식(1)의 PK(2의 누승값)를 {0, 1, …, M-1}의 부분집합들에서 선택하여 SM,L을 구함으로써 종래방법과 동일한 계수로 표현할 때는 약25%~33%정도 간단해진 쉬프터를 구현 가능할 뿐만 아니라 약간의 성능저하를 감수하면 50%이상 쉬프터를 줄일 수 있어 디지탈신호처리에 사용되는 필터의 주요부분인 곱셈기를 쉬프터와 덧셈기로 대체할 수 있는 2의 누승계수를 갖는 곱셈기가 필요없는 FIR 필터의 구현방법이다.In this case, P K (the power of 2) of the formula (1) is represented by {0, 1,... When, as well as it is implemented from about 25% to 33% degree simplified shifter when expressed as a rank equal to the conventional method taking a slight performance degradation by calculating the S M, L and chosen from a subset of the M-1} 50 It is an implementation method of FIR filter that does not need a multiplier with a power factor of 2 to replace the multiplier which is the main part of the filter used for digital signal processing with the shifter and the adder because it can reduce the shifter by more than%.

Description

프로그램 가능한 2의 누승계수를 갖는 곱셈기가 필요없는 FIR 필터의 구현방법How to Implement a Programmable Multiplier with a Multiplier of 2 Without a FIR Filter

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도 (a)는 본 발명에 따른 2PFIR 필터의 전체 구조도, 제1도 (b)는 본 발명에 따른 2PFIR 필터의 탭의 구조도, 제2도는 N×(M-2L+2)비트 쉬프터를 사용한 PK∈ZK인 2PFIR 필터의 구조도, 제3도는 2PFIR 필터의 덧셈 형태를 나타낸 그래프.Figure 1 (a) is the overall structural diagram of the 2PFIR filter according to the present invention, Figure 1 (b) is a structural diagram of the tap of the 2PFIR filter according to the present invention, Figure 2 is N × (M-2L + 2) bits Structure diagram of a 2PFIR filter of P K ∈ Z K using a shifter, and FIG. 3 is a graph showing the addition form of the 2PFIR filter.

Claims (4)

양의 정수 M과 L에 대하여 2PFIR 필터의 계수 h(n)이For positive integers M and L, the coefficient h (n) of the 2PFIR filter 이라 할 때, 상기 식(1)의 PK(2의 누승값)를 {0, 1, …, M-1}의 부분집합들에서 선택하여 SM,L을 구함으로써 각 쉬프터(shifter)의 길이를 2(L-1)만큼씩 줄이는 것을 특징으로 하는 프로그램 가능한 2의 누승계수를 갖는 곱셈기가 필요없는 FIR 필터의 구현방법.In this case, P K (the power of 2) of the formula (1) is represented by {0, 1,... , A multiplier with a power factor of 2, characterized in that the length of each shifter is reduced by 2 (L-1) by selecting from the subsets of M-1} to find S M, L. How to implement an unnecessary FIR filter. 제1항에 있어서, 쉬프터(shifter)로서 쉬프트 레지스터(shift register)를 사용한 경우 쉬프터 레지스터의 길이를 2(L-1)만큼 줄여 처리속도를 증가시키는 것을 특징으로 하는 프로그램 가능한 2의 누승계수를 갖는 곱셈기가 필요없는 FIR 필터의 구현방법.2. The programmable power factor of claim 1, wherein when a shift register is used as a shifter, the processing speed is increased by reducing the length of the shifter register by 2 (L-1). How to implement a FIR filter that does not require a multiplier. 제1항에 있어서, 쉬프터(shifter)로서 배럴쉬프트(barral shifter)를 사용한 경우 배럴시프터의 길이를 2(L-1)만큼 줄여 하드웨어의 복잡도를 감소시키는 것을 특징으로 하는 프로그램 가능한 2의 누승계수를 갖는 곱셈기가 필요없는 FIR 필터의 구현방법.The programmable power factor of 2 according to claim 1, wherein when the barrel shifter is used as a shifter, the complexity of the hardware is reduced by reducing the length of the barrel shifter by 2 (L-1). A method of implementing an FIR filter that does not require a multiplier. 제1항에 있어서, PK가 임의의 i, j, i≠j에 대하여The method of claim 1, wherein P K is for any i, j, i ≠ j |Pi-Pj|≥2 (2)| P i -P j | ≥2 (2) 만족하도록 하여 2PFIR 필터의 각 계수들을 CSD(cannonical signde digit)코드로 표현함으로써 쉬프터의 길이를 줄이는 것을 특징으로 하는 프로그램 가능한 2의 누승계수를 갖는 곱셈기가 필요없는 FIR 필터의 구현방법.A method of implementing a multiplier without a multiplier having a power of 2, characterized by reducing the length of the shifter by expressing each coefficient of the 2PFIR filter in a canonical signde digit (CSD) code. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930014360A 1993-07-27 1993-07-27 Power-of-two fir filter KR960014183B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100823252B1 (en) * 2002-11-07 2008-04-21 삼성전자주식회사 OFDM based Timing Synchronization apparatus and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100823252B1 (en) * 2002-11-07 2008-04-21 삼성전자주식회사 OFDM based Timing Synchronization apparatus and method

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