KR940027169A - Capacitor Formation Method of Semiconductor Device Having Double Structure Electrode - Google Patents

Capacitor Formation Method of Semiconductor Device Having Double Structure Electrode Download PDF

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KR940027169A
KR940027169A KR1019930008838A KR930008838A KR940027169A KR 940027169 A KR940027169 A KR 940027169A KR 1019930008838 A KR1019930008838 A KR 1019930008838A KR 930008838 A KR930008838 A KR 930008838A KR 940027169 A KR940027169 A KR 940027169A
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South Korea
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film
polysilicon film
electrode
oxide film
forming
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KR1019930008838A
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Korean (ko)
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KR960011663B1 (en
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유의규
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 이중구조 전극을 갖는 반도체 장치의 캐패시터 형성방법에 관한 것으로, 반도체기판 상에 필드산화막을 형성하고, 게이트산화막과 게이트전극 및 워드선을 형성하고, 스페이서 산화막을 이용한 LDD(Lightly Doped Drain)구조의 활성영역을 갖는 MOSFET을 형성한 다음 일정 두께의 절연산화막을 증착하고, 상기 산화막을 식각해 MOSFET의 활성영역의 어느 한편에 콘택홀을 형성한 다음, 불순물이 주입된 1차 전하보존전극 폴리실리콘막을 증착하는 제1 단계. 상기 1차 전하보존전극 폴리실리콘막상에 일정두께의 희생산화막과 마스크 폴리실리콘막을 차례로 증착하고, 상기 마스크 폴리실리콘막을 선택식각한 다음, 다시 폴리실리콘막을 증착한 후 식각하여 스페이서 폴리실리콘막을 형성하는 제2단계, 상기 마스크 폴리실리콘막과 스페이서 폴리실리콘막을 식각 마스크로 상기 희생산화막을 선택식각하여 콘택홀을 형성하는 제3단계, 상기 콘택홀을 통하여 불순물이 주입된 2차 전하보존전극 폴리실리콘막을 증착해 1차 전하보존전극 폴리실리콘막과 접속시키고, 마스크를 이용해 2차 전하보존전극 폴리실리콘막과 마스크 폴리실리콘막을 선택적으로 식각한 다음, 감광막이 도포된 상태에서 노출되어진 희생산화막을 습식식각하여 상기 희생산화막의 일부인 공동영역을 형성하는 제4단계 및 , 상기 1차 전하보존전극 폴리실리콘막을 소정 크기로 식각하고, 감광막을 제거한 다음, 상기 전하보존전극의 표면을 따라 유전막을 형성하고, 상기 유전막 상에 불순물이 주입된 폴리실리콘막을 증착한 다음, 소정 크기로 식각해 플래이트전극을 형성하는 제5단계를 포함하여 이루어지는 것을 특징으로 함으로써, 전하보존용량을 증가시켜 DRAM 셀등의 기억장치 제작에 이용될 경우, 소자의 신뢰성 향상의 효과를 얻을 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor of a semiconductor device having a double structure electrode, wherein a field oxide film is formed on a semiconductor substrate, a gate oxide film, a gate electrode and a word line are formed, and a lightly doped drain (LDD) using a spacer oxide film is provided. After forming a MOSFET having an active region of a structure, an insulating oxide film having a predetermined thickness is deposited, and the oxide film is etched to form a contact hole in one of the active regions of the MOSFET, and then an impurity-implanted primary charge storage electrode poly The first step of depositing a silicon film. Depositing a sacrificial oxide film having a predetermined thickness and a mask polysilicon film on the primary charge preservation electrode polysilicon film in order, selectively etching the mask polysilicon film, and then depositing a polysilicon film and then etching to form a spacer polysilicon film A second step of forming a contact hole by selectively etching the sacrificial oxide layer using the mask polysilicon film and the spacer polysilicon film as an etch mask, and depositing a secondary charge preservation electrode polysilicon film into which impurities are injected through the contact hole The secondary charge preservation electrode polysilicon film and the mask polysilicon film are selectively etched by using a mask, and then the wetted sacrificial oxide film is wet-etched while the photoresist film is applied. A fourth step of forming a cavity region which is part of the sacrificial oxide film, and the primary charge The preservation electrode polysilicon film is etched to a predetermined size, the photoresist film is removed, a dielectric film is formed along the surface of the charge preservation electrode, a polysilicon film implanted with impurities is deposited on the dielectric film, and then the substrate is etched to a predetermined size. By including the fifth step of forming an electrode, when the charge storage capacity is increased to be used for manufacturing a memory device such as a DRAM cell, it is possible to obtain an effect of improving the reliability of the device.

Description

이중구조 전극을 갖는 반도체 장치의 캐패시터 형성방법Capacitor Formation Method of Semiconductor Device Having Double Structure Electrode

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 이중구조 전극 캐패시터 형성 공정 단면도.2 is a cross-sectional view of a dual structure electrode capacitor forming process according to the present invention.

Claims (4)

이중구조 전극을 갖는 반도체 장치의 캐패시터 형성방법에 있어서, 반도체기판(1)상에 필드산화막(2)을 형성하고, 게이트산화막(3) 과 게이트전극(4) 및 워드선(4')을 형성하고, 스페이서 산화막(5)을 이용한 LDD(Lightly Doped Drain)구조의 활성영역(6,6')을 갖는 MOSFET을 형성한 다음 일정 두께의 절연산화막(7)을 증착하고, 상기 산화막을 식각해 MOSFET의 활성영역(6)의 어느 한편에 콘택홀을 형성한 다음, 불순물이 주입된 1차 전하보존전극 폴리실리콘막(8)을 증착하는 제1단계, 상기 1차 전하보존전극 폴리실리콘막(8)상에 일정두께의 희생 산호막(9) 과 마스크 폴리실리콘막(10)을 선택식각한 다음, 다시 폴리실리콘막을 증착한 후 식각하여 스페이서 폴리실리콘막(11)을 형성하는 제2단계, 상기 마스크 폴리실리콘막(10)과 스페이서 폴리실리콘막(11)을 식각 마스크로 상기 희생산화막(9)을 선택식각하여 콘택홀을 형성하는 제3단계, 상기 콘택홀을 통하여 불순물이 주입된 2차 전하보존전극 폴리실리콘막(12)을 증착해 1차 전하보존전극 폴리실리콘막(8)과 접속시키고, 마스크를 이용해 2차 전하보존전극 폴리실리콘막(12) 과 마스크 폴리실리콘막(10)을 선택적으로 식각한 다음, 감광막(13) 이 도포된 상태에서 노출되어진 희생산화막(9)을 습식식각하여 상기 희생산화막(9) 의 일부인 공동영역(16)을 형성하는 제4단계 및, 상기 1차 전하보존전극 폴리실리콘막(8)을 소정 크기로 식각하고, 감광막(13)을 제거한 다음, 상기 전하보존전극의 표면을 따라 유전막(14)을 형성하고, 상기 유전막 상에 불순물이 주입된 폴리실리콘막을 증착한 다음, 소정 크기로 식각해 플래이트전극(15)을 형성하는 제5단계를 포함하여 이루어지는 것을 특징으로 하는 이중구조 전극을 갖는 반도체 장치의 캐패시터 형성방법.In the method for forming a capacitor of a semiconductor device having a double structure electrode, a field oxide film 2 is formed on a semiconductor substrate 1, and a gate oxide film 3, a gate electrode 4, and a word line 4 'are formed. Next, a MOSFET having an active region (6,6 ') of a lightly doped drain (LDD) structure using a spacer oxide film 5 is formed, and then an insulating oxide film 7 having a predetermined thickness is deposited, and the oxide film is etched to form a MOSFET. Forming a contact hole in one of the active regions 6 and then depositing a primary charge storage electrode polysilicon film 8 into which impurities are implanted, and the primary charge storage electrode polysilicon film 8 A second step of selectively etching the sacrificial coral film 9 and the mask polysilicon film 10 on a predetermined thickness, and then depositing a polysilicon film and then etching to form a spacer polysilicon film 11. The mask polysilicon film 10 and the spacer polysilicon film 11 are etch masks. A third step of forming a contact hole by selectively etching the sacrificial oxide film 9, and depositing a secondary charge preservation electrode polysilicon film 12 into which impurities are injected through the contact hole to deposit a primary charge preservation electrode polysilicon film (8), the secondary charge storage electrode polysilicon film 12 and the mask polysilicon film 10 are selectively etched using a mask, and then the sacrificial oxide film exposed in the state where the photosensitive film 13 is applied ( A fourth step of wet etching 9) to form a cavity region 16 which is a part of the sacrificial oxide film 9, and etching the primary charge preservation electrode polysilicon film 8 to a predetermined size and then photosensitive film 13 A fifth layer for forming a dielectric film 14 along the surface of the charge preserving electrode, depositing a polysilicon film in which impurities are implanted on the dielectric film, and etching to a predetermined size to form the plate electrode 15. It is characterized by what is done, including steps A capacitor forming a semiconductor device having a double structure electrode according to. 제1항에 있어서, 상기 1차전하보존전극 폴리실리콘막(8)은 인접한 워드선(4') 과 게이트전극(4)까지 확장되어 덮여있는 것을 특징으로 하는 이중구조 전극을 갖는 반도체 장치의 캐패시터 형성방법.2. The capacitor of claim 1, wherein the primary charge storage electrode polysilicon film 8 extends and covers the adjacent word line 4 'and the gate electrode 4, respectively. Formation method. 제1항에 있어서, 상기 제4단계의 희생산화막(9)은 PSG막으로 형성하는 것을 특징으로 하는 이중구조 전극을 갖는 반도체 장치의 캐패시터 형성방법.2. The method of claim 1, wherein the sacrificial oxide film (9) of the fourth step is formed of a PSG film. 제1항에 있어서, 상기 제5단계의 유전막(14)은 질화막-산화막(NO ; nitride oxide)또는 산화막-질화막-산화막(ONO ; oxide nitride oxide) 복합구조의 유전막임을 특징으로 하는 이중구조 전극을 갖는 반도체 장치의 캐패시터 형성방법.The dual layer electrode of claim 1, wherein the dielectric film 14 of the fifth step is a dielectric film having a nitride-oxide oxide (NO) or oxide-nitride oxide (ONO) composite structure. A method for forming a capacitor of a semiconductor device having. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930008838A 1993-05-21 1993-05-21 Capacitor manufacturing method of semiconductor device double electrode KR960011663B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100328743B1 (en) * 1995-11-28 2002-10-31 삼성전자 주식회사 Ferroelectric dynamic random access memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100328743B1 (en) * 1995-11-28 2002-10-31 삼성전자 주식회사 Ferroelectric dynamic random access memory

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