KR960006716B1 - Semiconductor integrated circuit device fabrication process - Google Patents
Semiconductor integrated circuit device fabrication process Download PDFInfo
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- KR960006716B1 KR960006716B1 KR1019920026934A KR920026934A KR960006716B1 KR 960006716 B1 KR960006716 B1 KR 960006716B1 KR 1019920026934 A KR1019920026934 A KR 1019920026934A KR 920026934 A KR920026934 A KR 920026934A KR 960006716 B1 KR960006716 B1 KR 960006716B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 title description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 104
- 229920005591 polysilicon Polymers 0.000 claims abstract description 104
- 238000003860 storage Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000004321 preservation Methods 0.000 claims description 32
- 239000012535 impurity Substances 0.000 claims description 22
- 125000006850 spacer group Chemical group 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 17
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000005360 phosphosilicate glass Substances 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims description 2
- 239000012528 membrane Substances 0.000 claims 1
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000002131 composite material Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 101100290380 Caenorhabditis elegans cel-1 gene Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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Abstract
Description
제1도는 종래의 방법에 의한 DRAM 형성도,1 is a diagram illustrating DRAM formation by a conventional method,
제2도는 본 발명에 따른 일실시예의 DRAM 제조 공정도.2 is a DRAM manufacturing process diagram of an embodiment according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1 : 반도체기판 2 : 필드산화막1: semiconductor substrate 2: field oxide film
3 : 게이트산화막 4 : 게이트전극3: gate oxide film 4: gate electrode
5 : 워드선 6 : 장벽산화막5: word line 6: barrier oxide film
7 : 스페이서 산화막 8,8' : MOSFET 활성영역7 spacer oxide film 8,8 'MOSFET active area
9,11,16 : 산화막 10 : 1차 전하보존 전극 폴리실리콘막9,11,16 oxide film 10 primary charge preservation electrode polysilicon film
12,17 : BPSG막 13,20 : 마스크폴리실리콘막12,17 BPSG film 13,20 Mask polysilicon film
14,22' : 스페이서폴리실리콘막 15 : 폴리사이드14,22 ': spacer polysilicon film 15: polyside
18 : 2차전하보존전극폴리실리콘막 19,21 : 희생산화막18: secondary charge preservation electrode polysilicon film 19, 21: sacrificial oxide film
22 : 폴리실리콘막 23 : 3차전하보존전극폴리실리콘막22 polysilicon film 23 tertiary charge preservation electrode polysilicon film
24 : 감광막 25 : 유전막24: photosensitive film 25: dielectric film
26 : 플래이트전극.26: plate electrode.
본 발명은 충분한 전하보존 용량을 확보할 수 있는 DRAM(Dynmic RAM)에 관한 것이다.The present invention relates to a DRAM (Dynmic RAM) capable of securing a sufficient charge storage capacity.
일반적으로 반도체 메모리 소자인 DRAM의 집적화와 관련해 중요한 요인으로는 셀(Cel1)의 면적 감소와 이에 따른 전하보존 용량 확보의 한계등을 들 수 있다. 그러나 반도체 집적회로의 고집적화를 달성하기 위해서 칩(Chip)과 셀의 단위면적의 감소는 필연적이고, 이에 따라 고도의 공정기술의 개발과 함께 단위소자의 신뢰성 확보와 셀의 전하보존 용량 확보는 절실한 해결과제가 되고 있다.In general, an important factor related to the integration of DRAM, which is a semiconductor memory device, may include a reduction in the area of the cell Cel1 and a limitation of securing charge storage capacity. However, in order to achieve high integration of semiconductor integrated circuits, it is inevitable to reduce the unit area of chips and cells. Therefore, with the development of advanced process technology, securing the reliability of unit devices and securing the charge storage capacity of cells are urgent solutions. It becomes a problem.
종래의 DRAM 제조방법을 제1도를 통하여 살펴보면, 도면에서 1은 반도체 기판,2는 필드 산화막, 3은 게이트 산화막, 4는 게이트 전극, 5는 워드선, 7은 스페이서 산화막, 8,8'는 MOSFET 활성영역, 11,16은산화막, 12,17은 BPSG막, 13,20은 마스크 폴리실리콘막, 14는 스페이서 폴리실리콘막, 15는 폴리사이드, 18은 2차 전하보존 전극 폴리실리콘막, 22는 폴리실리콘막, 25는 유전막, 26은 플래이트 전극을 각각 나타낸다.Referring to FIG. 1, a conventional DRAM manufacturing method is shown in FIG. 1, where 1 is a semiconductor substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a gate electrode, 5 is a word line, 7 is a spacer oxide film, and 8,8 ' MOSFET active region, 11 and 16 oxide film, 12 and 17 BPSG film, 13 and 20 mask polysilicon film, 14 spacer polysilicon film, 15 polyside, 18 secondary charge preservation electrode polysilicon film, 22 Is a polysilicon film, 25 is a dielectric film, and 26 is a plate electrode.
도면에 도시된 바와 같이 반도체 기판(1)에 필드산화막(2)을 형성하고, 게이트 산화막(3), 게이트 전극(4) 및 워드선(5) 패턴을 형성한 다음에 고집적화에 따른 MOSFET의 전기적 특성을 개선하기 위해 스페이서 산화막(7)을 이용한 LDD구조의 활성영역(8,8')을 갖는 MOSFET 형성공정을 실시한다. 이어서 고온산화방법으로 제1절연 산화막(11)과 제1BPSG막(12)을 차례로 형성하고, 활성영역(8)위에 제1마스크 폴리실리콘막(13)과 제1스페이서 폴리실리콘막(14)을 이용한 자기정렬 방식으로 콘택 홀을 형성하고, 이 콘택 홀위에 불순물이 주입된 폴리실리콘막과 실리사이드막을 차례로 증착한 폴리사이드막(15)을 활성영역(8)과 접속시키고, 마스크를 이용해 소정의 크기로 비트선(15) 패턴을 형성한다. 계속해서 고온 산화방법의 제2 절연 산화막(16)과 제2BPSG막(17)을 증착하고, 활성영역(8')위에 제2 마스크 폴리실리콘막(20)과 제 2스페이서 폴리실리콘막(22)을 이용한 자기정렬 방식으로 콘택 홀을 형성하여, 이 콘택 홀위에 불순물이 주입된 1차 전하보존 전극 폴리실리콘막(18)을 증착시켜 활성영역(8')과 접속시켜 전하보존 전극 패턴을 형성한다. 이어서 NO 또는 ONO복합구조의 유전막(25)을 성장시키고, 그 위에 불순물이 주입된 폴리실리막을 이용해 플래이트 전극(26)을 갖는 커패시터(Capacitor)를 구성해 기존의 DRAM 셀의 주요 공정을 완료하게 된다.As shown in the figure, the field oxide film 2 is formed on the semiconductor substrate 1, the gate oxide film 3, the gate electrode 4 and the word line 5 pattern are formed. In order to improve the characteristics, a MOSFET forming process having the active regions 8 and 8 'of the LDD structure using the spacer oxide film 7 is performed. Subsequently, the first insulating oxide film 11 and the first BSPSG film 12 are sequentially formed by a high temperature oxidation method, and the first mask polysilicon film 13 and the first spacer polysilicon film 14 are formed on the active region 8. A contact hole is formed by a self-aligning method, and a polysilicon film 15 in which an impurity-implanted polysilicon film and a silicide film are sequentially deposited is connected to the active region 8 with a predetermined size using a mask. The bit line 15 pattern is formed. Subsequently, the second insulating oxide film 16 and the second BPSG film 17 of the high temperature oxidation method are deposited, and the second mask polysilicon film 20 and the second spacer polysilicon film 22 are formed on the active region 8 '. A contact hole is formed by a self-aligning method using the same, and a primary charge preservation electrode polysilicon film 18 into which impurities are injected is deposited on the contact hole, and is connected to the active region 8 'to form a charge preservation electrode pattern. . Subsequently, a dielectric film 25 having a NO or ONO composite structure is grown, and a capacitor having a plate electrode 26 is formed by using a polysilicon film implanted with impurities thereon to complete a main process of a conventional DRAM cell. .
그러나 상기 종래의 DRAM구조는 반도체 집적회로의 현재의 공정능력을 감안할때, 고집적으로 갈수록 전하보존 전극의 축전 용량에 한계점을 나타내고 있으며, 소자의 신뢰도를 떨어뜨리는 문제점이 있었다.However, in view of the current process capability of the semiconductor integrated circuit, the conventional DRAM structure shows a limit on the storage capacity of the charge storage electrode as the density becomes higher, and there is a problem of lowering the reliability of the device.
따라서, 상기 문제점을 해결하기 위해 안출된 본 발명은 충분한 캐패시터 용량을 확보하여 고집적 소자를 실현하는 DRAM 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a DRAM manufacturing method for realizing a highly integrated device by securing sufficient capacitor capacity.
상기 목적을 달성하기 위하여 본 발명은, 반도체 집적회로의 제조방법에 있어서, 반도체 기간에 필드 산화막을 형성하고, 게이트 산화막과 불순물 이온 주입된 폴리실리콘막을 차례로 증착한후에 상기 폴리실리콘막위에 장벽 산화막을 증착시키고, 마스크를 이용해 상기 폴리실리콘과 장벽 산화막을 패턴하여 게이트전극을 형성한 다음에 저농도 불순물 이온 주입, 스페이서 산화막 형성, 고농도 불순물 이온주입을 행하여 LDD구조의 활성영역을 갖는 MOSFET을 형성하는 제1단계와, 제1산화막을 증착하고 상기 제1산화막을 선택식각해 상기 MOSFET의 활성영역의 어느 한쪽에 콘택 홀을 형성하고, 불순물이 주입된 폴리실리콘을 증착하여 소정의 크기로 1차 전하보존 전극 폴리실리콘막을 형성하는 제2단계와, 제2산화막, 제1BPSG막, 제 1마스크 폴리실리콘막을 차례로 증착하고 상기 제 1마스크 폴리실리콘막과 약간의 제1BPSG막을 식각한 다음에 감광막을 제거한 상태에서 폴리실리콘을 증착하고, 이를 비등방성으로 식각해 제1스페이서 폴리실리콘막을 형성하여 상기 활성영역(8)에 콘택 홀을 형성하고 폴리사이드를 증착하여 비트선 형성하는 제3단계와, 제3산화막과 제2BPSG막을 차례로 증착하고 상기 1차 전하보존 전극 폴리실리콘막위에 콘택 홀을 형성하여 이 콘택 홀에 불순물이 주입된 2차 전하보존 전극 폴리실리콘막(18)을 증착하는 제4단계와,제1희생 산화막, 제2마스크 폴리실리콘막, 제2희생 산화막을 차례로 증착하고, 마스크를 이용해 상기 제2희생 산화막, 제2마스크 폴리실리콘막, 제1희생 산화막상부를 식각하여 감광막을 제거한 상태에서 폴리실리콘막을 증착하고 비등방성으로 식각 제2스페이서 폴리실리콘막을 형성하는 제5단계와, 식각이 되지않은 상기 제2마스크 폴리실리콘막과 제2스페이서 폴리실리콘막을 이용해 상기 2차 전하보존 전극 폴리실리콘막에 자기정렬형 콘택 홀을 형성하고, 이 콘택 홀에 불순물이 주입된 3차 전하보존 전극 폴리실리콘막을 증착 후에 소정의 크기로 상기 3차 전하보존 전극 폴리실리콘막과 제2마스크 폴리실리콘막을 차례로 선택 식각하고, 감광막이 존재하는 상태로 상기 제1희생 산화막의 습식식각과 2차 전하보존 전극 폴리실리콘의 건식식각을 차례로 행하여 3층 구조의 전하보존 전극을 형성하는 제6단계와, 감광막을 제거하고 유전막을 성장시킨 다음, 폴리실리콘을 증착하고, 이를 소정의 크기로 식각해 플래이트 전극을 형성하는 제7단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor integrated circuit, wherein a field oxide film is formed in a semiconductor period, and a barrier oxide film is deposited on the polysilicon film after the gate oxide film and the impurity ion implanted polysilicon film are sequentially deposited. And forming a gate electrode by patterning the polysilicon and the barrier oxide film using a mask, followed by low concentration impurity ion implantation, spacer oxide film formation, and high concentration impurity ion implantation to form a MOSFET having an active region of an LDD structure. And depositing a first oxide film, selectively etching the first oxide film to form a contact hole in one of the active regions of the MOSFET, and depositing polysilicon implanted with impurities to deposit a first charge preservation electrode poly with a predetermined size. A second step of forming a silicon film, a second oxide film, a first BPSG film, and a first mask polysilicon film For example, after the deposition, the first mask polysilicon layer and the first 1BPSG layer are etched, and then the polysilicon is deposited in a state where the photoresist layer is removed. A third step of forming a contact hole in the contact hole and depositing a polyside to form a bit line, and then depositing a third oxide film and a second BPSG film, and forming a contact hole on the primary charge preservation electrode polysilicon film. Depositing a second charge preservation electrode polysilicon film 18 impregnated with impurities, and then depositing a first sacrificial oxide film, a second mask polysilicon film, and a second sacrificial oxide film, and then using a mask Etch the sacrificial oxide film, the second mask polysilicon film, and the first sacrificial oxide film to remove the photosensitive film, and then deposit a polysilicon film and then anisotropically etch the second spacer pole. Forming a silicon film, and forming a self-aligned contact hole in the secondary charge preservation electrode polysilicon film using the second mask polysilicon film and the second spacer polysilicon film which are not etched, and the contact hole After depositing the third charge preservation electrode polysilicon film into which the impurity is implanted, the third charge preservation electrode polysilicon film and the second mask polysilicon film are sequentially selected and etched in a predetermined size, and the first sacrificial film is present in the state where the photoresist film is present. Wet etching of the oxide film followed by dry etching of the secondary charge preservation electrode polysilicon in order to form a charge preservation electrode having a three-layer structure, removing the photoresist, growing the dielectric film, and depositing polysilicon And forming a plate electrode by etching to a predetermined size.
이하, 편의상 DRAM 셀의 게이트 전극과 수직인 방향의 단면만 표시한 제2도를 참조하여 본 발명에 따른 일실시예를 설명하면, 도면에서 1은 반도체 기판,2는 필드 산화막,3은 게이트 산화막,4는 게이트 전극,5는 워드선,6은 장벽 산화막,7은 스페이서 산화막,8,8'는 MOSFET 활성영역,9,11,16은 산화막,10은 1차 전하보존 전극 폴리실리콘막,12,17은 BPSG막,13,20은 마스크 폴리실리콘막,14,22'는 스페이서 폴리실리콘막,15는 폴리사이드,18은 2차 전하보존 전극 폴리실리콘막,19,21은 희생 산화막,22는 폴리실리콘막,23은 3차 전하보존 전극 폴리실리콘막,24는 감광막,25는 유전막,26은 플래이트 전극을 각각 나타낸다.Hereinafter, for convenience, an embodiment according to the present invention will be described with reference to FIG. 2, which only shows a cross section in a direction perpendicular to the gate electrode of a DRAM cell. In the drawings, 1 is a semiconductor substrate, 2 is a field oxide film, and 3 is a gate oxide film. 4 is a gate electrode, 5 is a word line, 6 is a barrier oxide, 7 is a spacer oxide, 8,8 'is a MOSFET active region, 9, 11, 16 is an oxide film, 10 is a primary charge preservation electrode polysilicon film, 12 17 is a BPSG film, 13 and 20 is a mask polysilicon film, 14 and 22 'is a spacer polysilicon film, 15 is a polyside, 18 is a secondary charge preservation electrode polysilicon film, and 19 and 21 is a sacrificial oxide film. The polysilicon film, 23 is a tertiary charge storage electrode polysilicon film, 24 is a photosensitive film, 25 is a dielectric film, and 26 is a plate electrode.
먼저, 제2도(a)는 반도체 웨이퍼(1)위에 LOCOS(Local Oxidati on of Silicon) 방식으로 필드 산화막(2)을 성장하고, 게이트 산화막(3)을 형성한 후에 지연시간 없이 폴리실리콘막을 증착해 불순물 주입 공정을 행한 다음 장벽 산화막(6)을 증착하고 사진식각을 이용해 상기 산화막(6)과 폴리실리콘막을 선택적으로 식각하여 게이트 전극(4) 및 워드선(5)을 형성한 후에 상대적으로 저농도인 N형(또는 P형) 불순물을 이온주입한 다음에 스페이서 산화막(7)을 형성하고, 상대적으로 고농도인 N형(또는 P형) 불순물 이온주입을 행하여 LDD 구조의 활성영역(8,8')을 갖는 MOSFET을 형성한 상태의 단면도이다.First, in FIG. 2A, a field oxide film 2 is grown on a semiconductor wafer 1 by LOCOS (Local Oxidati on of Silicon), a polysilicon film is deposited without a delay after the gate oxide film 3 is formed. After the impurity implantation process, the barrier oxide film 6 is deposited, and the oxide film 6 and the polysilicon film are selectively etched using photolithography to form the gate electrode 4 and the word line 5, and then relatively low concentration. Phosphorus N-type (or P-type) impurity is ion-implanted, then a spacer oxide film 7 is formed, and relatively high concentrations of N-type (or P-type) impurity ion implantation are performed to form active regions 8,8 'of the LDD structure. It is sectional drawing of the state which formed MOSFET which has).
제 2 도(b) 는 제 1 산화막(9) 을 증착하고 MOSFET의 활성 영역 (8') 상의 상기 제 1 산화막(9) 을 제거하여 콘택 홀을 형성한 후에 불순물이 주입된 1차 전하보존 전극 폴리실리콘막(10)을 증착하여 소정의 크기로 패턴한 상태의 단면도이다. 여기서 상기 제1산화막(9)은 1차 전하보존 전극 폴리실리콘막(10)을 식각할 때 MOSFET의 다른 활성영역(8)을 보호하는 역할을 한다.FIG. 2 (b) shows a primary charge storage electrode in which impurities are implanted after depositing a first oxide film 9 and removing the first oxide film 9 on the active region 8 'of the MOSFET to form a contact hole. It is sectional drawing of the state which patterned the polysilicon film 10 to predetermined size. Here, the first oxide film 9 serves to protect the other active region 8 of the MOSFET when the primary charge preservation electrode polysilicon film 10 is etched.
제2도(c)는 고온 산화방법으로 일정두께의 절연 제2산화막(11)과 제1BPSG막(12)을 차례로 증착하고,고온의 평탄화 공정을 행한 후 그위에 일정두께의 제 1마스크 폴리실리콘막(13)을 증착하고, 상기 제 1마스크 폴리실리콘막(13)과 약간의 BPSG막을 식각한 다음에 일정두께의 폴리실리콘을 증착시켜 비등방성 방식으로 식각해 제1스페이서 폴리실리콘막(14)을 형성한 단면도로서, 계속하여 폴리실리콘막과 BPSG막의 식각 선택비를 이용한 자기 정렬 방식으로 MOSFET의 활성영역(8)위에 콘택 홀을 형성하고, 이 콘택 홀을 동하여 불순물이 주입된 폴리실리콘과 실리사이드를 차례로 증착한 폴리사이드(15)를 활성영역(8)과 접속시켜 소정의 크기로 패턴하여 비트선(l5)을 형성한 단면도이다.FIG. 2 (c) illustrates a step of depositing an insulating second oxide film 11 and a first BSPG film 12 having a predetermined thickness by a high temperature oxidation method, and performing a planarization process at a high temperature, followed by a first mask polysilicon having a predetermined thickness thereon. The film 13 is deposited, the first mask polysilicon film 13 and some BPSG films are etched, and then polysilicon having a predetermined thickness is deposited to be etched in an anisotropic manner to etch the first spacer polysilicon film 14. And a contact hole is formed on the active region 8 of the MOSFET in a self-aligning manner using the etching selectivity of the polysilicon film and the BPSG film, and the impurity is injected into the contact hole. A polyline 15 in which silicides are sequentially deposited is connected to the active region 8 to be patterned to a predetermined size to form a bit line l5.
제2도(d)는 소자간 절연을 위해 고온 산화방법으로 일정두께의 제3산화막(16), 제2BPSG막(17)을 차례로 증착하고, 전면 식각으로 평탄화 공정을 행한 후에 전하보존 콘택 홀 마스크를 이용해 상기 제3산화막(16)과 제2BPSG막(17)을 차례로 선택 식각하여 상기 1차 전하보존 전극 폴리실리콘막(10)위에 콘택 홀을 형성한 단면도이다. 그리고, 계속하여 상기 콘택 홀을 통하여 1차 전하보존 전극 폴리실리콘막(10)과 접속되도록 불순물이 주입된 2차 전하보존 전극 폴리실리콘막(18)을 증착한 상태의 단면도이다. 여기서 상기제3산화막(16)을 증착후에 후속 고온 열치리 공정을 통하여 상기 제1마스크 폴리실리콘막(13)과 제1스페이서 폴리실리콘막(14)은 불순물이 확산되어 폴리사이드(15)와 함께 비트선 역할을 하게 된다.FIG. 2 (d) shows the charge preservation contact hole mask after depositing the third oxide film 16 and the second BPSG film 17 having a predetermined thickness by using a high temperature oxidation method in order to insulate the devices, and performing a planarization process by etching the entire surface. A cross-sectional view of forming a contact hole on the first charge preservation electrode polysilicon film 10 by selectively etching the third oxide film 16 and the second BPSG film 17 by using. Subsequently, a cross-sectional view of a state in which a secondary charge preservation electrode polysilicon film 18 in which an impurity is implanted is subsequently deposited is connected to the primary charge preservation electrode polysilicon film 10 through the contact hole. The first mask polysilicon layer 13 and the first spacer polysilicon layer 14 may be diffused together with the polyside 15 by depositing the third oxide layer 16 and subsequent high temperature thermal treatment. It acts as a bit line.
제2도(e)는, 일정두께의 제 1희생 산화막(19), 제 2 마스크 폴리실리콘(20), 식각장애용 제 2 희생 산화막(21)을 차례로 증착하고, 상기 제2희생 산화막(21), 제2마스크 폴리실리콘(20), 제1희생 산화막(19) 상부 일부를 차례로 식각한 다음에 감광막을 제거하고, 그위에 일정두께의 폴리실리콘막(22)을 증착시킨 상태의 단면도이다. 이때 상기 제1희생 산화막은 폴리실리콘에 비해 높은 선택식각비를 갖는 PSG(Phospho Silicate Glass)막으로 구성하게 된다.FIG. 2E sequentially deposits a first sacrificial oxide film 19 having a predetermined thickness, a second mask polysilicon 20, and a second sacrificial oxide film 21 for etching disorder, and then the second sacrificial oxide film 21. ), A second mask polysilicon 20, and a portion of the upper portion of the first sacrificial oxide film 19 are sequentially etched, the photosensitive film is removed, and a polysilicon film 22 having a predetermined thickness is deposited thereon. In this case, the first sacrificial oxide film is composed of a PSG (Phospho Silicate Glass) film having a higher selectivity than the polysilicon.
제2도(f)는 상기 폴리실리콘막(22)을 비등방성 방식으로 식각해 스페이서 폴리실리콘막(22')을 형성하고, 폴리실리콘막과 산화막의 식각 선택비를 이용한 자기정렬 방식으로 2차 전하보존 전극 폴리실리콘(16)위에 콘택 홀을 형성하고, 이 콘택 홀을 동하여 2차 전하보존 전극 폴리실리큰(18)과 접속되도록 불순물이 주입된 3차 전하보존 전극 폴리실리콘(23)을 증착시킨 단면도로서, 계속하여 상기 3차 전하보존 전극 폴리실리콘막(23)과 제2폴리실리콘막(26)을 차례로 식각하고, 감광막(24)이 있는 상태에서 상기 2차 전하보존전극 폴리실리콘막(18)을 장벽으로 해서 희생 산화막(19)을 습식식각한 후에 계속해서 2차 전하보존 전극폴리실리콘(18)을 건식식각해서 3층 구조의 전하보존 전극을 형성한 단면도이다. 여기서 상기 스페이서 폴리실리콘막(22')을 형성할때, 상기 제2도(e)의 제2산화막(21)은 장벽역할을 해서 제2마스크 폴리실리콘막(20)이 식각되지 않도록 하여 밑의 충돌을 보호하는 역할을 한다.FIG. 2 (f) shows that the polysilicon layer 22 is etched in an anisotropic manner to form a spacer polysilicon layer 22 ', and is secondary in a self-aligning manner using an etching selectivity ratio between the polysilicon layer and the oxide layer. A contact hole is formed on the charge storage electrode polysilicon 16, and the contact hole is moved to form a third charge storage electrode polysilicon 23 into which impurities are injected so as to be connected to the secondary charge storage electrode polysilicon 18. As a cross-sectional view of the deposition, the third charge preservation electrode polysilicon film 23 and the second polysilicon film 26 are sequentially etched, and the secondary charge preservation electrode polysilicon film is present with the photosensitive film 24 present. After wet etching the sacrificial oxide film 19 using (18) as a barrier, the secondary charge storage electrode polysilicon 18 is subsequently dry etched to form a charge storage electrode having a three-layer structure. Here, when the spacer polysilicon film 22 'is formed, the second oxide film 21 of FIG. 2E serves as a barrier so that the second mask polysilicon film 20 is not etched. It serves to protect against collisions.
제2도(g) 상기 제1희생 산화막(19)을 삭각해 전하보존 전극의 유효면적을 포함하는 전하보존 전극을따라 NO(Nitride-Oxide) 또는 ONO(Oxide-Nitride-Oxide) 복합구조의 유전막(25)을 성장시키고, 상기 유전막(24)위에 불순물이 주입된 폴리실리콘막을 증착한 다음에 마스크를 이용 소정의 크기로 폴리실리콘을 식각해 플레이트 전극(26)을 형성함으로 본 발명에 의한 전하보전 캐패시터를 갖는 새로운 구조의 DRAM 셀 공정이 완성된 상태의 단면도이다. 여기서 상기 유전막(25)을 성장시키는 등의 열공정으토 통하여 상기 제2마스크 폴리실리콘막(20)과 제2스페이서 폴리실리콘막(22')은 불순물이 확산되어 1,2,3차 전하보존 전극 폴리실리콘막(10,18,23)과 함께 전하보존 전극 역활을 하게 된다.FIG. 2 (g) is a dielectric film of NO (Nitride-Oxide) or ONO (Oxide-Nitride-Oxide) composite structure along the charge storage electrode including the effective area of the charge storage electrode by cutting off the first sacrificial oxide film 19 (25) growing, depositing a polysilicon film impregnated with impurities on the dielectric film 24, and then etching the polysilicon to a predetermined size using a mask to form a plate electrode 26, the charge preservation according to the present invention It is sectional drawing of the DRAM cell process of the new structure which has a capacitor completed. Here, the second mask polysilicon film 20 and the second spacer polysilicon film 22 'are diffused with impurities through thermal processes such as the growth of the dielectric film 25 to form the 1,2,3rd charge preservation electrode. Together with the polysilicon films 10, 18, and 23, they serve as charge storage electrodes.
상기와 같이 이루어지는 본 발명의 DRAM 셀은 전하보존 용량을 증가시켜 소자의 신뢰성을 향상시킬 수있으며, 공정측면에서도 1차 전하보존 전극 폴리실리콘을 사용하여 보다 넓은 콘택 홀의 면적을 확보할 수있으므로 기존의 기술만으로도 3층의 전하보존 전극의 형성이 가능한 공정단순화의 효과가 있다.The DRAM cell of the present invention made as described above can improve the reliability of the device by increasing the charge storage capacity, and in terms of the process, it is possible to secure a larger contact hole area by using the primary charge storage electrode polysilicon. The technology alone has the effect of a process simplification that enables the formation of three layers of charge storage electrodes.
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