KR940015850A - Circuitry to implement the flag signals needed for the control of gunpo - Google Patents
Circuitry to implement the flag signals needed for the control of gunpo Download PDFInfo
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- KR940015850A KR940015850A KR1019920026156A KR920026156A KR940015850A KR 940015850 A KR940015850 A KR 940015850A KR 1019920026156 A KR1019920026156 A KR 1019920026156A KR 920026156 A KR920026156 A KR 920026156A KR 940015850 A KR940015850 A KR 940015850A
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Abstract
본 발명은 FIFO(First-In First-Out)콘트롤을 위해 필요한 플래그 신호를 구현하는 회로에 관한 것으로, 인버터(3)을 통해 반전된 WR신호가 입력되는 프리세트 단자, 클럭 신호를 받는 클럭단자, 인버터(4)를 통해 반전된 UP-fiag신호가 입력되는 클리어 단자, WR-flag신호를 출력하는 출력 단자, 상기 출력 WR-flag가 피드백(feed back)되어 입력되어지는 입력단자로 구성되는 하나의 D플립플롭(7)과, 인버터(5)를 통해 반전된 RD신호가 입력되는 프리세트 단자, 클럭 신호가 입력되는 클럭 단자, 인버터(6)을 통해 반전된 DOWN-flag가 입력되는 클리어 단자, RD-flag를 출력 하는 출력단자, 상기 출력 DOWN-flag가 피드백 되어 입력되어지는 입력단자를 갖는 또하의 D플립플롭(8)으로 구성되어 지는 것을 특징으로 하는 FIFO제어를 위해 필요한 플래그 신호를 구현하는 회로에 관한 것이다.The present invention relates to a circuit for implementing a flag signal required for FIFO (First-In First-Out) control, a preset terminal to which the inverted WR signal is input through the inverter 3, a clock terminal receiving a clock signal, A clear terminal to which the inverted UP-fiag signal is input through the inverter 4, an output terminal to output the WR-flag signal, and an input terminal to which the output WR-flag is fed back and inputted A preset terminal to which the D flip-flop 7 and the inverted RD signal are input through the inverter 5, a clock terminal to which the clock signal is input, a clear terminal to which the inverted DOWN-flag is input through the inverter 6, An output terminal for outputting an RD-flag, and another D flip-flop (8) having an input terminal fed back to the output DOWN-flag to implement a flag signal necessary for FIFO control It is about a circuit.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 본 발명에 따른 FIFO콘트롤 블럭도, 제2도는 본 발명에 따른 FIFO의 쓰기시의 타이밍도, 제4도는 본 발명에 따른 FIFO콘트롤 로직 회로도.1 is a FIFO control block diagram according to the present invention, FIG. 2 is a timing diagram when a FIFO is written according to the present invention, and FIG. 4 is a FIFO control logic circuit diagram according to the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920026156A KR940015850A (en) | 1992-12-29 | 1992-12-29 | Circuitry to implement the flag signals needed for the control of gunpo |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920026156A KR940015850A (en) | 1992-12-29 | 1992-12-29 | Circuitry to implement the flag signals needed for the control of gunpo |
Publications (1)
Publication Number | Publication Date |
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KR940015850A true KR940015850A (en) | 1994-07-21 |
Family
ID=67214792
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920026156A KR940015850A (en) | 1992-12-29 | 1992-12-29 | Circuitry to implement the flag signals needed for the control of gunpo |
Country Status (1)
Country | Link |
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KR (1) | KR940015850A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100403396B1 (en) * | 1995-12-06 | 2004-03-31 | 사이프러스 세미컨덕터 코포레이션 | Device for generating output flag indicating fullness of FIFO buffer |
-
1992
- 1992-12-29 KR KR1019920026156A patent/KR940015850A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100403396B1 (en) * | 1995-12-06 | 2004-03-31 | 사이프러스 세미컨덕터 코포레이션 | Device for generating output flag indicating fullness of FIFO buffer |
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