KR940015706A - Method of manufacturing measurement mark in mask pattern of semiconductor device - Google Patents

Method of manufacturing measurement mark in mask pattern of semiconductor device Download PDF

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Publication number
KR940015706A
KR940015706A KR1019920024542A KR920024542A KR940015706A KR 940015706 A KR940015706 A KR 940015706A KR 1019920024542 A KR1019920024542 A KR 1019920024542A KR 920024542 A KR920024542 A KR 920024542A KR 940015706 A KR940015706 A KR 940015706A
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KR
South Korea
Prior art keywords
outer box
semiconductor device
box
measurement mark
mask pattern
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Application number
KR1019920024542A
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Korean (ko)
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KR960007621B1 (en
Inventor
문승찬
이철승
배상만
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019920024542A priority Critical patent/KR960007621B1/en
Publication of KR940015706A publication Critical patent/KR940015706A/en
Application granted granted Critical
Publication of KR960007621B1 publication Critical patent/KR960007621B1/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

본 발명은 반도체 소자의 마스크 패턴시 측정마크 제조방법에 관한 것으로, 중첩 정확도를 측정하는 측정장비를 이용하여 측정할 수 있도록 마스크 제작시 박스인박스 형태로 측정마크를 형성하여 정확한 중첩정확도를 측정하여 공정오차를 최대한으로 감소시키는 측정마크 제조방법이다.The present invention relates to a method of manufacturing a measurement mark in the mask pattern of a semiconductor device, by forming a measurement mark in the form of a box-in-box when manufacturing a mask to be measured using a measuring device for measuring the overlapping accuracy by measuring the exact accuracy of the overlapping It is a method of manufacturing a measurement mark that reduces process errors to the maximum.

Description

반도체 소자의 마스크패턴시 측정마크 제조방법Method of manufacturing measurement mark in mask pattern of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의하여 형성된 측정마크의 중첩정확도 측정원리를 나타낸 평면도, 제2A도 내지 제2D도는 본 발명의 실시예에 의하여 형성된 여러가지 형태의 측정마크를 도시한 단면도, 제2E도는 본 발명에 의하여 형성된 측정마크중 가장 일반적인 구조를 도시한 평면도 및 단면도, 제3A도 내지 제3C도는 반도체 칩(chip)의 형태에 따른 측정마크의 배치를 나타낸 평면도.1 is a plan view showing the measurement accuracy of the superposition accuracy of the measurement mark formed by the present invention, Figures 2A to 2D is a cross-sectional view showing the measurement marks of various forms formed by the embodiment of the present invention, Figure 2E is a 3A through 3C are plan views showing the arrangement of measurement marks according to the shape of a semiconductor chip.

Claims (7)

반도체 소자의 마스크 패턴시 측정마크 제조방법에 있어서, 패턴 형성공정시 패턴과 패턴간의 중첩 정확도를 향상시키기 위하여 스크라이브 라인에 측정마크를 형성하되, 4각형 안쪽박스와 4각형 바깥박스 형태의 패턴구조를 마스크 패턴 공정에서 중첩되도록 형성하여, 그로인하여 측정장비를 이용하여 중첩 정확도를 측정하도록 하는 것을 특징으로 하는 반도체 소자의 마스크 패턴시 측정마크 제조방법.In the method of manufacturing a measurement mark at the mask pattern of a semiconductor device, a measurement mark is formed on a scribe line in order to improve the accuracy of overlapping between the pattern and the pattern during the pattern formation process. Formed to overlap in the mask pattern process, thereby measuring the overlap accuracy by using a measuring device to measure the measurement mark at the mask pattern of the semiconductor device. 제1항에 있어서, 상기 바깥박스는 사각형 요부형태로 형성하고, 상기 안쪽박스는 사각형 철부형태로 형성하되, 바깥박스의 중앙부에 바깥박스보다 작은 면적으로 안쪽박스를 형성하는 것을 특징으로 하는 반도체 소자의 마스크 패턴시 측정마크 제조방법.The semiconductor device of claim 1, wherein the outer box is formed in a rectangular recess, and the inner box is formed in a rectangular convex shape, and the inner box is formed in a central portion of the outer box with a smaller area than the outer box. Method of manufacturing a measurement mark when the mask pattern. 제1항에 있어서, 상기 바깥박스는 사각형 철부형태로 형성하고, 상기 안쪽박스는 상기 바깥박스의 중앙부에 바깥박스보다 작은 면적으로 형성하는 것을 특징으로 하는 반도체 소자의 마스크 패턴시 측정마크 제조방법.The method of claim 1, wherein the outer box is formed in the shape of a rectangular convex portion, and the inner box is formed at a central portion of the outer box with a smaller area than the outer box. 제1항에 있어서, 상기 안쪽박스는 사각형 요부형태로 형성하고, 상기 바깥박스는 상기 안쪽박스보다 큰 면적으로 안쪽박스 가장자리 상부에 사각형 요부형태로 형성하는 것을 특징으로 하는 반도체 소자의 마스크 패턴시 측정 마크 제조방법.The semiconductor device of claim 1, wherein the inner box is formed in a rectangular recess, and the outer box is formed in a rectangular recess on an upper edge of the inner box with a larger area than the inner box. Mark production method. 제1항, 제2항, 제3항 또는 제4항에 있어서, 상기 바깥박스의 물질과 안쪽박스의 물질은 서로 다른 것을 특징으로 하는 반도체 소자의 마스크 패턴시 측정마크 제조방법.5. The method of claim 1, wherein the material of the outer box and the material of the inner box are different from each other. 6. 제5항에 있어서, 상기 바깥박스의 물질이 폴리실리콘 또는 절연층일때 안쪽박스의 물질은 감광막으로 형성하거나, 상기 바깥박스의 물질이 감광막일때 안쪽박스의 물질이 폴리실리콘 또는 절연층으로 형성하는 것을 특징으로 하는 반도체 소자의 마스크 패턴시 측정마크 제조방법.The method of claim 5, wherein the material of the inner box is formed of a photoresist film when the material of the outer box is polysilicon or insulating layer, or the material of the inner box is formed of polysilicon or insulation layer when the material of the outer box is photosensitive film Method for manufacturing a measurement mark in the mask pattern of a semiconductor device characterized in that. 제1항에 있어서, 상기 측정마크는 칩 가장자리의 사각모서리 또 일부모서리에 다수개 배열하는 것을 특징으로 하는 반도체 소자의 마스크 패턴시 측정마크 제조방법.The method of claim 1, wherein a plurality of measurement marks are arranged at a square edge or a partial edge of a chip edge. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920024542A 1992-12-17 1992-12-17 Method of compensating for overlaying error in semiconductor device KR960007621B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920024542A KR960007621B1 (en) 1992-12-17 1992-12-17 Method of compensating for overlaying error in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920024542A KR960007621B1 (en) 1992-12-17 1992-12-17 Method of compensating for overlaying error in semiconductor device

Publications (2)

Publication Number Publication Date
KR940015706A true KR940015706A (en) 1994-07-21
KR960007621B1 KR960007621B1 (en) 1996-06-07

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100353820B1 (en) * 1995-12-16 2003-01-24 주식회사 하이닉스반도체 Method for forming vernier of semiconductor device
KR100680936B1 (en) * 2000-01-07 2007-02-08 주식회사 하이닉스반도체 Align checking method of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100353820B1 (en) * 1995-12-16 2003-01-24 주식회사 하이닉스반도체 Method for forming vernier of semiconductor device
KR100680936B1 (en) * 2000-01-07 2007-02-08 주식회사 하이닉스반도체 Align checking method of semiconductor device

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Publication number Publication date
KR960007621B1 (en) 1996-06-07

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