KR940008013B1 - Manufacturing method of silicon thin film - Google Patents

Manufacturing method of silicon thin film Download PDF

Info

Publication number
KR940008013B1
KR940008013B1 KR1019910000481A KR910000481A KR940008013B1 KR 940008013 B1 KR940008013 B1 KR 940008013B1 KR 1019910000481 A KR1019910000481 A KR 1019910000481A KR 910000481 A KR910000481 A KR 910000481A KR 940008013 B1 KR940008013 B1 KR 940008013B1
Authority
KR
South Korea
Prior art keywords
silicon
thin film
depositing
heat treatment
islands
Prior art date
Application number
KR1019910000481A
Other languages
Korean (ko)
Other versions
KR920015432A (en
Inventor
최종문
Original Assignee
금성일렉트론 주식회사
문정환
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성일렉트론 주식회사, 문정환 filed Critical 금성일렉트론 주식회사
Priority to KR1019910000481A priority Critical patent/KR940008013B1/en
Publication of KR920015432A publication Critical patent/KR920015432A/en
Application granted granted Critical
Publication of KR940008013B1 publication Critical patent/KR940008013B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02516—Crystal orientation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Thin Film Transistor (AREA)

Abstract

The method includes the steps of depositing a first amorphous silicon on a thermal oxide layer and performing a first heat treatment to form a silicon islands having respective crystal face, depositing a second amorphous silicon on a thermal oxide layer on which first silicon island is formed and performing a second heat treatment to form a silicon layer having respective crystal face on between the silicon islands, selectively etching the silicon layer, depositing a third amorphous silicon on a thermal oxide layer on which first silicon island and silicon layer are formed and performing a third heat treatment to make the silicon recrystallized, thereby obtaining silicon thin film having excellent characteristics.

Description

실리콘 박막 제조방법Silicon thin film manufacturing method

제 1 도는 종래 박막형 트랜지스터의 개략도.1 is a schematic diagram of a conventional thin film transistor.

제 2 도는 본 발명의 실리콘 박막 제조공정을 나타낸 단면도로서2 is a cross-sectional view showing a silicon thin film manufacturing process of the present invention.

제 3 도의 a,b는 본 발명에 따른 실리콘박막을 이용한 트랜지스터의 구조도.3 is a structural diagram of a transistor using a silicon thin film according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 게이트 11 : 게이트 산화물10 gate 11 gate oxide

12 : 채널부 13 : 절연체12 channel portion 13 insulator

14 : 실리콘기판 20 : 산화막14 silicon substrate 20 oxide film

30 : 비정질 실리콘 31 : 실리콘섬30: amorphous silicon 31: silicon island

본 발명은 실리콘 박막 제조방법에 관한 것으로, 특히 박막형 트랜지스터에 적당하도록 한 실리콘 박막의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing a silicon thin film, and more particularly to a method for producing a silicon thin film suitable for a thin film transistor.

종래의 실리콘박막 제조방법은 제 1 도에 도시한 바와 같이 절연체(13) 위에 Si2H4가스를 소오스로 하여 LPCVD방법에 의해 실리콘 박막(12)을 80-500Å의 두께로 증착시키고 600-800℃의 온도로 장시간 열처리함으로써 실리콘의 결정립 크기를 크게 한다.In the conventional silicon thin film manufacturing method, as shown in FIG. 1, Si 2 H 4 gas is used as the source on the insulator 13, and the silicon thin film 12 is deposited to a thickness of 80-500 kV by LPCVD. The heat treatment at a temperature of 占 폚 for a long time increases the grain size of silicon.

이와 같이 실리콘의 결정립을 크게 하고 게이트 절연막(11)을 형성한 다음 게이트 전극(10)과 소오스 및 드레인 영역을 형성하여 트랜지스터를 만들었다.As described above, the silicon grains were enlarged, the gate insulating layer 11 was formed, and then the transistor was formed by forming the gate electrode 10 and the source and drain regions.

따라서 종래 실리콘 박막 제조방법은 채널부의 결정립수를 최대한 줄이므로써 결정임계에 의한 특성저하를 감소시키도록 하였다.Therefore, the conventional silicon thin film manufacturing method is to reduce the decrease in characteristics due to the crystal threshold by reducing the number of grains in the channel portion as much as possible.

그러나 채널부의 결정립수를 감소시켰으나 채널부의 결정임계가 존재하게 되므로 트랜지스터의 누설전류가 많이 흐르게 되고 안정동작에 문제가 있는 단점이 있었다.However, the number of crystal grains in the channel portion is reduced, but the crystal threshold of the channel portion is present, so that a large amount of leakage current flows in the transistor and there is a problem in the stable operation.

본 발명은 상기한 단점을 개선하기 위한 것으로 채널영역에 결정임계가 존재하지 않는 단결정 실리콘을 형성하는 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above-described disadvantages, and an object of the present invention is to provide a method for forming single crystal silicon having no crystal threshold in a channel region.

이와 같은 목적을 달성하기 위한 본 발명은 열산화막 위에 실리콘 섬 형태로 제 1 비정질 실리콘을 얇게 증착시키고 1차 열처리하여 각각 다른 결정학적 면을 갖는 단결정 실리콘 섬을 형성시킨 공정과, 상기 단결정 실리콘 섬이 형성된 전면에 제 2 비정질 실리콘을 증착시키고 2차 열처리하여 상기 단결정 실리콘 섬 사이에 다른 결정학적 면을 갖는 실리콘 형성하는 공정과, 상기 실리콘을 식각하여 부분적으로 남기는 공정과, 전면에 제 3 비정질 실리콘을 증착하고 3차 열처리하여 재 결정시키는 공정을 포함하여 이루어짐을 특징으로 하는 실리콘 박막 제조방법으로 이루어진 것이다.The present invention for achieving the above object is a process of thinly depositing first amorphous silicon in the form of silicon islands on the thermal oxide film and the first heat treatment to form a single crystal silicon island having a different crystallographic plane, and the single crystal silicon island Depositing a second amorphous silicon on the formed front surface and performing a second heat treatment to form silicon having a different crystallographic surface between the single crystal silicon islands, etching the silicon partially to leave the third amorphous silicon on the front surface It is made of a silicon thin film manufacturing method comprising the step of depositing and recrystallization by the third heat treatment.

이와 같은 본 발명을 첨부된 도면을 참조하여 보다 상세히 설명하면 다음과 같다. 제 2 도는 본 발명의 실리콘 박막 공정 단면도로서, 먼저 열산화막 표면과 CVD산화막 표면을 비교해 보면, CVD산화막 표면에 비해 열산화막 표면이 본질적으로 치밀한 구조를 갖고 있으므로 평탄하여 CVD산화막 보다 증착속도가 느리다.When described in more detail with reference to the accompanying drawings, the present invention as follows. 2 is a cross-sectional view of the silicon thin film process of the present invention. First, when the surface of the thermal oxide film is compared with the surface of the CVD oxide film, the surface of the thermal oxide film is inherently more dense than the surface of the CVD oxide film, and thus is flat and slower than the CVD oxide film.

그러므로 CVD산화막 보다 열산화막 위에서 실리콘을 증착하면 박막을 얻을 수 있다.Therefore, a thin film can be obtained by depositing silicon on a thermal oxide film rather than a CVD oxide film.

따라서 제 2 도 a와 같이 열산화막(20) 위에 500-580℃의 온도에 Si2H4가스를 소오스로 하여 LPCVD방법으로 약 50-100Å정도의 비정질 실리콘(30)을 증착 시킨다.Thus also the second depositing a thermal oxide film 20, the amorphous silicon (30) of about 50-100Å the LPCVD method, the Si 2 H 4 gas as a source to a temperature of 500-580 ℃ above, such as a.

이때 비정질 실리콘(30)이 얇게 증착되므로 실리콘 섬 모양으로 증착된다.At this time, since the amorphous silicon 30 is thinly deposited, it is deposited in a silicon island shape.

그리고, 비정질 실리콘(30)은 600-750℃의 온도에서 열처리하여 제 4 도의 b에 도시한 바와 같이 각각 다른 결정학적 면을 갖는 단결정 실리콘 섬(31)을 형성시킨다.The amorphous silicon 30 is then heat treated at a temperature of 600-750 ° C. to form single crystal silicon islands 31 having different crystallographic planes as shown in b of FIG. 4.

여기서, 각각의 단결정 실리콘 섬(31)은 체적이 매우 작고 단결화가 용이하며 600℃에서 12시간 이상 충분히 열처리하면 모두 단결정이 된다.Here, each of the single crystal silicon islands 31 is very small in volume, easy to unite, and all become single crystals when sufficiently heat treated at 600 DEG C for at least 12 hours.

제 2 도 c와 같이 상기 단결정실리콘 섬(31) 위에 500-580℃의 온도에서 다시 Si2H4가스를 소오스로 하여 LPCVD방법으로 약 150-250Å의 두께를 갖도록 비정질 실리콘을 재 증착시켜 600-750℃의 온도로 재 결정화시키면 실리콘섬과 실리콘섬 사이의 열산화막 위에 다른 결정학적 면을 갖는 실리콘이 형성된다.As shown in FIG. 2C, amorphous silicon is re-deposited to have a thickness of about 150-250 Pa by LPCVD using Si 2 H 4 gas as a source again at a temperature of 500-580 ° C. on the single crystal silicon island 31. Recrystallization at a temperature of 750 ° C. results in the formation of silicon with a different crystallographic face on the thermal oxide film between the silicon island and the silicon island.

이때 형성된 실리콘 박막은 몇개의 결정학적면을 갖는 실리콘 결정으로 구성되며 실리콘박막을 결정학적 식각을 하면 결정방향에 따라 식각속도가 다르므로 결국 제일 안정된 면을 갖는 결정방향의 실리콘 섬만 남게 된다.In this case, the formed silicon thin film is composed of silicon crystals having several crystallographic planes. When the silicon thin film is crystallographically etched, the etching rate varies depending on the crystallization direction, and thus only the silicon islands in the crystallographic direction having the most stable plane remain.

따라서 제 2 도 d와 같이 실리콘을 식각하면, 제일 안정된 면을 갖는 〈111〉방향의 실리콘 섬만 선택적으로 남는다.Therefore, as shown in FIG. 2, when silicon is etched, only silicon islands in the < 111 > direction having the most stable surface remain selectively.

이때 결정학적 면지수(111)면을 갖는 실리콘 섬(32)에 비정질 실리콘(21)을 500-580℃의 온도에 다시 증착하여 600-750℃의 온도에 재결정시키면 제 2 도 e와 같이 단결정 실리콘 박막을 얻을 수 있다.At this time, when the amorphous silicon 21 is deposited again on the silicon island 32 having the crystallographic surface index 111 surface at a temperature of 500-580 ° C and recrystallized at a temperature of 600-750 ° C, single crystal silicon is shown in FIG. A thin film can be obtained.

따라서 제 3 도는 본 발명의 실리콘 박막을 이용한 트랜지스터 구조도로서 본 발명에 의해 형성된 실리콘 박막위에 게이트 절연막과 게이트 전극(10)을 형성하고 소오스 및 드레인 이온주입하여 트랜지스터를 형성하면 채널부에 결정임계가 존재하지 않으므로서 누설전류가 감소하고 안정된 동작을 우수한 특성의 박막형 트랜지스터를 얻을 수 있는 효과가 있다.3 is a transistor structure diagram using the silicon thin film of the present invention, when the gate insulating film and the gate electrode 10 are formed on the silicon thin film formed by the present invention, and source and drain ions are implanted to form a transistor, a crystal threshold exists in the channel portion. Therefore, there is an effect that a thin film transistor having excellent characteristics can be obtained with a reduced leakage current and stable operation.

Claims (2)

열산화막 위에 실리콘 섬 형태로 제 1 비정질 실리콘을 얇게 증착시키고 1차 열처리하여 각각 다른 결정학적 면을 갖는 단결정 실리콘 섬을 형성시킨 공정과, 상기 단결정 실리콘 섬이 형성된 전면에 제 2 비정질 실리콘을 증착시키고 2차 열처리하여 상기 단결정 실리콘 섬 사이에 다른 결정학적 면을 갖는 실리콘을 형성하는 공정과, 상기 실리콘을 식각하여 부분적으로 남기는 공정과, 전면에 제 3 비정질 실리콘을 증착하고 3차 열처리하여 재 결정시키는 공정을 포함하여 이루어짐을 특징으로 하는 실리콘 박막 제조방법.Depositing a thin layer of first amorphous silicon in the form of silicon islands on the thermal oxide film and performing a first heat treatment to form single crystal silicon islands having different crystallographic planes, and depositing second amorphous silicon on the entire surface where the single crystal silicon islands are formed. Forming a silicon having a different crystallographic surface between the single crystal silicon islands by secondary heat treatment, etching the silicon partially to leave the silicon, and depositing third amorphous silicon on the entire surface and recrystallization by tertiary heat treatment. Method for producing a silicon thin film, characterized in that comprises a step. 제 1 항에 있어서, 제 1 비정질 실리콘은 50-100Å의 두께로 증착하여 제 2 비정질실리콘은 150-250Å의 두께로 증착함을 특징으로 하는 실리콘 박막 제조방법.The method of claim 1, wherein the first amorphous silicon is deposited to a thickness of 50-100 kPa and the second amorphous silicon is deposited to a thickness of 150-250 kPa.
KR1019910000481A 1991-01-15 1991-01-15 Manufacturing method of silicon thin film KR940008013B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910000481A KR940008013B1 (en) 1991-01-15 1991-01-15 Manufacturing method of silicon thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910000481A KR940008013B1 (en) 1991-01-15 1991-01-15 Manufacturing method of silicon thin film

Publications (2)

Publication Number Publication Date
KR920015432A KR920015432A (en) 1992-08-26
KR940008013B1 true KR940008013B1 (en) 1994-08-31

Family

ID=19309769

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910000481A KR940008013B1 (en) 1991-01-15 1991-01-15 Manufacturing method of silicon thin film

Country Status (1)

Country Link
KR (1) KR940008013B1 (en)

Also Published As

Publication number Publication date
KR920015432A (en) 1992-08-26

Similar Documents

Publication Publication Date Title
US4441249A (en) Semiconductor integrated circuit capacitor
JPS59159563A (en) Manufacture of semiconductor device
US5433168A (en) Method of producing semiconductor substrate
US4868140A (en) Semiconductor device and method of manufacturing the same
KR940008013B1 (en) Manufacturing method of silicon thin film
JP2593898B2 (en) Semiconductor element
JPH0738118A (en) Manufacture of thin film transistor
JPS63146436A (en) Manufacture of thin film transistor
JP2720473B2 (en) Thin film transistor and method of manufacturing the same
KR960004902B1 (en) Preparation of polycrystalline silicon thin film
JPH034564A (en) Manufacture of semiconductor device
JP2794833B2 (en) Method for manufacturing thin film transistor
KR970011502B1 (en) Thin film transistor manufacturing method
JP3325664B2 (en) Thin film transistor and method of manufacturing the same
JPH0669430A (en) Manufacture of semiconductor device
JP3065528B2 (en) Semiconductor device
JPS6266619A (en) Manufacture of semiconductor device
KR0127316B1 (en) Oxydation method of poly-silicon
JP3153202B2 (en) Method for manufacturing semiconductor device
KR0151273B1 (en) Method of manufacturing thin film transistor
KR940006666B1 (en) Manufactruing method for polysilicon film
JPH05299657A (en) Field effect thin film transistor element
KR0167239B1 (en) Method of isolation film on a semiconductor device
KR0167257B1 (en) Method of forming an isolation on a semiconductor device
KR100312980B1 (en) A method of forming field oxide

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090727

Year of fee payment: 16

LAPS Lapse due to unpaid annual fee