KR930022525A - Semiconductor assembly device - Google Patents
Semiconductor assembly device Download PDFInfo
- Publication number
- KR930022525A KR930022525A KR1019920006221A KR920006221A KR930022525A KR 930022525 A KR930022525 A KR 930022525A KR 1019920006221 A KR1019920006221 A KR 1019920006221A KR 920006221 A KR920006221 A KR 920006221A KR 930022525 A KR930022525 A KR 930022525A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor assembly
- semiconductor
- chip
- package body
- semiconductor chip
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
본 발명은 반도체 조립장치에 관한 것으로, 신호연결단자인 다수개의 본드패드(11a)를 주변부에 갖는 반도체칩(11)과, 상기 반도체 칩(11)을 다이 어태치하기 위한 요홈부(12a)가 형성됨과 아울러 주변부에는 상기 반도체칩(11)에 와이어 본딩되는 다수개의 도전패턴(12b)이 등간격으로 배열된 소정 형태의 패키지 몸체(12)와, 다이어 태치된 상기 칩(11)의 각 본드패드(11a)와 패키지 몸체(12)에 형성된 각각의 도전패턴(12b)을 전기적으로 접속 연결하기 위한 접속부재(13)와, 와이어 본딩된 상기 칩(11)과 패키지 몸체(12)의 상면을 포함하는 일정부분을 밀폐시키기 위한 절연수지로 구성된다. 이와같이된 본 발명의 반도체 조립장치는 리드프레임이 제거되므로 패키지의 경박단소화에 기여함을 물론 최근 다핀 파인 피치화되어 가고 있는 디바이스의 패키징에 적합하며, 제조공정을 간소화시킬 수 있는 등의 효과가 있다.The present invention relates to a semiconductor assembly device, wherein a semiconductor chip (11) having a plurality of bond pads (11a) as signal connection terminals at its periphery, and a recess (12a) for die attaching the semiconductor chip (11) A plurality of conductive patterns 12b that are wire-bonded to the semiconductor chip 11 are formed on the periphery thereof, and a package body 12 having a predetermined shape is arranged at equal intervals, and each bond pad of the die-attached chip 11 is formed. And a connecting member 13 for electrically connecting and connecting the conductive patterns 12b formed on the package body 12 and the upper surface of the wire-bonded chip 11 and the package body 12. It consists of insulating resin for sealing a certain part. The semiconductor assembly device of the present invention thus eliminates the lead frame, thereby contributing to light and small size reduction of the package, and is suitable for the packaging of devices having recently been made with a multi-pin fine pitch, and can simplify the manufacturing process. have.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도 및 제3도는 본 발명에 의한 반도체 조립장치에 사용되는 패키지 몸체의 구조를 보인 도면으로서, 제2도는 평면도, 제3도는 제2도의 A-선 단면도.2 and 3 are views showing the structure of the package body used in the semiconductor assembly apparatus according to the present invention, in which FIG. 2 is a plan view, and FIG. 3 is an A-line cross-sectional view of FIG.
제4도의 (a) (b) (c)는 본 발명에 의한 반도체 조립장치의 구조 및 제작과정을 설명하기 위한 제조 공정도.Figure 4 (a) (b) (c) is a manufacturing process diagram for explaining the structure and manufacturing process of the semiconductor assembly apparatus according to the present invention.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920006221A KR950000516B1 (en) | 1992-04-14 | 1992-04-14 | Semiconductor assembly device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920006221A KR950000516B1 (en) | 1992-04-14 | 1992-04-14 | Semiconductor assembly device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930022525A true KR930022525A (en) | 1993-11-24 |
KR950000516B1 KR950000516B1 (en) | 1995-01-24 |
Family
ID=19331772
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920006221A KR950000516B1 (en) | 1992-04-14 | 1992-04-14 | Semiconductor assembly device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR950000516B1 (en) |
-
1992
- 1992-04-14 KR KR1019920006221A patent/KR950000516B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR950000516B1 (en) | 1995-01-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7247944B2 (en) | Connector assembly | |
KR920010853A (en) | Resin-sealed semiconductor device | |
KR960043137A (en) | Method of manufacturing semiconductor device and semiconductor device and method of manufacturing lead frame | |
US4951120A (en) | Lead frame and semiconductor device using the same | |
US5804871A (en) | Lead on chip semiconductor device having bus bars and crossing leads | |
KR950007068A (en) | Method for manufacturing stacked semiconductor device and semiconductor package thereof | |
KR930022525A (en) | Semiconductor assembly device | |
KR0163524B1 (en) | Ball grid array package formed conducting pattern on the inner face of cap type package body | |
KR100218335B1 (en) | Chip-sized package | |
MY106858A (en) | Resin sealing type semiconductor device in which a very small semiconductor chip is sealed in package with resin. | |
KR960005965A (en) | Semiconductor devices | |
US6323541B1 (en) | Structure for manufacturing a semiconductor die with copper plated tapes | |
KR100401536B1 (en) | Method for altering center pad type semiconductor chip to peripheral pad type semiconductor chip | |
KR970053649A (en) | Wireless Semiconductor Package | |
KR930009028A (en) | Semiconductor package using interconnect lead and manufacturing method thereof | |
KR950007011Y1 (en) | Plastic packaging type | |
KR100213435B1 (en) | Master electrode pad of semiconductor chip and tap package using it | |
JPH0366150A (en) | Semiconductor integrated circuit device | |
KR0124547Y1 (en) | Semiconductor device for multi-type lead frame | |
KR100525091B1 (en) | semiconductor package | |
KR950010866B1 (en) | Surface mounting type semiconductor package | |
KR970013233A (en) | Multi-chip package with center pad type chip using substrate | |
KR980012384A (en) | Lead frame with different inner lead edge | |
KR980006210A (en) | Board for Multichip Package with Added Test Pad | |
JPH0637131A (en) | Semiconductor integrated circuit device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20041230 Year of fee payment: 11 |
|
LAPS | Lapse due to unpaid annual fee |