KR930022525A - Semiconductor assembly device - Google Patents

Semiconductor assembly device Download PDF

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Publication number
KR930022525A
KR930022525A KR1019920006221A KR920006221A KR930022525A KR 930022525 A KR930022525 A KR 930022525A KR 1019920006221 A KR1019920006221 A KR 1019920006221A KR 920006221 A KR920006221 A KR 920006221A KR 930022525 A KR930022525 A KR 930022525A
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KR
South Korea
Prior art keywords
semiconductor assembly
semiconductor
chip
package body
semiconductor chip
Prior art date
Application number
KR1019920006221A
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Korean (ko)
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KR950000516B1 (en
Inventor
백영상
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019920006221A priority Critical patent/KR950000516B1/en
Publication of KR930022525A publication Critical patent/KR930022525A/en
Application granted granted Critical
Publication of KR950000516B1 publication Critical patent/KR950000516B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 반도체 조립장치에 관한 것으로, 신호연결단자인 다수개의 본드패드(11a)를 주변부에 갖는 반도체칩(11)과, 상기 반도체 칩(11)을 다이 어태치하기 위한 요홈부(12a)가 형성됨과 아울러 주변부에는 상기 반도체칩(11)에 와이어 본딩되는 다수개의 도전패턴(12b)이 등간격으로 배열된 소정 형태의 패키지 몸체(12)와, 다이어 태치된 상기 칩(11)의 각 본드패드(11a)와 패키지 몸체(12)에 형성된 각각의 도전패턴(12b)을 전기적으로 접속 연결하기 위한 접속부재(13)와, 와이어 본딩된 상기 칩(11)과 패키지 몸체(12)의 상면을 포함하는 일정부분을 밀폐시키기 위한 절연수지로 구성된다. 이와같이된 본 발명의 반도체 조립장치는 리드프레임이 제거되므로 패키지의 경박단소화에 기여함을 물론 최근 다핀 파인 피치화되어 가고 있는 디바이스의 패키징에 적합하며, 제조공정을 간소화시킬 수 있는 등의 효과가 있다.The present invention relates to a semiconductor assembly device, wherein a semiconductor chip (11) having a plurality of bond pads (11a) as signal connection terminals at its periphery, and a recess (12a) for die attaching the semiconductor chip (11) A plurality of conductive patterns 12b that are wire-bonded to the semiconductor chip 11 are formed on the periphery thereof, and a package body 12 having a predetermined shape is arranged at equal intervals, and each bond pad of the die-attached chip 11 is formed. And a connecting member 13 for electrically connecting and connecting the conductive patterns 12b formed on the package body 12 and the upper surface of the wire-bonded chip 11 and the package body 12. It consists of insulating resin for sealing a certain part. The semiconductor assembly device of the present invention thus eliminates the lead frame, thereby contributing to light and small size reduction of the package, and is suitable for the packaging of devices having recently been made with a multi-pin fine pitch, and can simplify the manufacturing process. have.

Description

반도체 조립장치Semiconductor assembly device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도 및 제3도는 본 발명에 의한 반도체 조립장치에 사용되는 패키지 몸체의 구조를 보인 도면으로서, 제2도는 평면도, 제3도는 제2도의 A-선 단면도.2 and 3 are views showing the structure of the package body used in the semiconductor assembly apparatus according to the present invention, in which FIG. 2 is a plan view, and FIG. 3 is an A-line cross-sectional view of FIG.

제4도의 (a) (b) (c)는 본 발명에 의한 반도체 조립장치의 구조 및 제작과정을 설명하기 위한 제조 공정도.Figure 4 (a) (b) (c) is a manufacturing process diagram for explaining the structure and manufacturing process of the semiconductor assembly apparatus according to the present invention.

Claims (4)

반도체 조립장치에 있어서, 신호연결단자인 다수개의 본드패드(11a)가 상면에 배열된 반도체 칩(11)과, 상기 반도체 칩(11)을 다이 어태치하기 위한 요홈부(12a)가 형성됨과 아울러 주변부에는 상기 반도체 칩(11)에 와이어 본딩되는 다수개의 도전패턴(12b)이 등간격으로 배열된 소정 형태의 패키지 몸체(12)와, 다이 어태치된 상기 칩(11)의 각 본드패드(11a)와 패키지몸체(12)에 형성된 가가의 도전패턴(12b)을 전기적으로 접속 연결하기 위한 접속부재(13)와, 와이어 본딩된 상기 칩(11)과 패키지 몸체(12)의 상면을 포함하는 일정부분을 밀폐시키기 위한 절연수지(14)로 구성됨을 특징으로하는 반도체 조립장치.In the semiconductor assembly apparatus, a semiconductor chip 11 having a plurality of bond pads 11a as signal connection terminals arranged on an upper surface thereof, and grooves 12a for die attaching the semiconductor chip 11 are formed. In the peripheral portion, a plurality of conductive patterns 12b wire-bonded to the semiconductor chip 11 are arranged at equal intervals, and each bond pad 11a of the die 11 is die-attached. ) And a connecting member 13 for electrically connecting and connecting the conductive conductive pattern 12b formed on the package body 12, and a wire bonded upper surface of the chip 11 and the package body 12. Semiconductor assembly device, characterized in that consisting of an insulating resin (14) for sealing the part. 제1항에 있어서, 상기 접속부재(13)는 전도성의 금속와이어인 것을 특징으로 하는 반도체 조립장치.The semiconductor assembly apparatus according to claim 1, wherein the connection member (13) is a conductive metal wire. 제1항에 있어서, 상기 접속부재(13)는 범프리드인 것을 특징으로 하는 반도체 조립장치.The semiconductor assembly apparatus according to claim 1, wherein the connection member is bumpless. 제1항에 있어서, 상기 접속부재(13)는 메탈라인이 형성된 절연테이프인 것을 특징으로 하는 반도체 조립장치.The semiconductor assembly apparatus according to claim 1, wherein the connection member (13) is an insulating tape having a metal line formed thereon. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920006221A 1992-04-14 1992-04-14 Semiconductor assembly device KR950000516B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920006221A KR950000516B1 (en) 1992-04-14 1992-04-14 Semiconductor assembly device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920006221A KR950000516B1 (en) 1992-04-14 1992-04-14 Semiconductor assembly device

Publications (2)

Publication Number Publication Date
KR930022525A true KR930022525A (en) 1993-11-24
KR950000516B1 KR950000516B1 (en) 1995-01-24

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Application Number Title Priority Date Filing Date
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KR950000516B1 (en) 1995-01-24

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