KR930009028A - Semiconductor package using interconnect lead and manufacturing method thereof - Google Patents
Semiconductor package using interconnect lead and manufacturing method thereof Download PDFInfo
- Publication number
- KR930009028A KR930009028A KR1019910017974A KR910017974A KR930009028A KR 930009028 A KR930009028 A KR 930009028A KR 1019910017974 A KR1019910017974 A KR 1019910017974A KR 910017974 A KR910017974 A KR 910017974A KR 930009028 A KR930009028 A KR 930009028A
- Authority
- KR
- South Korea
- Prior art keywords
- lead
- semiconductor chip
- semiconductor package
- interconnect
- inner lead
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 고안은 인터컨넥트 리드를 이용한 반도체 패키지 및 그 제조방법에 관한 것으로 반도체칩의 중앙부에 구비된 복수개의 본드패드와 리드프레임의 인너리드를 전기적으로 접속 연결하고 봉합하여 구성하는 반도체 패키지에 있어서, 상기 인너리드를 짧게 형성하고 그 인너리드와 반도체칩의 본드패드를 전기적으로 접속연결시키기 위한 인터컨넥트 리드를 상기 반도체칩의 상면에 부착하여 구성함을 특징으로 하고 있으며, 상기 인너컨넥트 리드는 상, 하절연판의 사이에 반도체칩의 본드패드와 연결되는 내부리드와, 리드프레임의 인너리드와 연결되는 외부리드가 구비된 복수개의 전도성 리드가 형성되어 있다.The present invention relates to a semiconductor package using an interconnect lead and a method of manufacturing the same. A semiconductor package comprising a plurality of bond pads provided at a central portion of a semiconductor chip and an inner lead of a lead frame, wherein the semiconductor package is electrically connected and sealed. An interconnect lead is formed on the upper surface of the semiconductor chip to shorten the inner lead and electrically connect the inner lead and the bond pad of the semiconductor chip. A plurality of conductive leads including an inner lead connected to the bond pad of the semiconductor chip and an outer lead connected to the inner lead of the lead frame are formed between the insulating plates.
이와같이 구성되는 본 발명은 리드프레임의 인너리드가 짧아 리드의 평면도 문제를 해결할 수 있고 제조공정이 단축되며 다핀의 DiP타입 패키지를 실현할 수 있는 등의 효과가 있다.The present invention configured as described above has the effect of shortening the inner lead of the lead frame to solve the plan problem of the lead, shortening the manufacturing process, and realizing a multi-pin DiP type package.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 의한 인터컨넥트 리드(interconncet-lid)를 이용한 반도체 패키지의 구성도,2 is a configuration diagram of a semiconductor package using an interconnect lead according to the present invention;
제3도는 본 발명에 사용되는 인터컨넥트 리드의 구성을 보이는 평면도.3 is a plan view showing the configuration of the interconnect lead used in the present invention.
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910017974A KR940008329B1 (en) | 1991-10-12 | 1991-10-12 | Semiconductor package using inter connect lead and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910017974A KR940008329B1 (en) | 1991-10-12 | 1991-10-12 | Semiconductor package using inter connect lead and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930009028A true KR930009028A (en) | 1993-05-22 |
KR940008329B1 KR940008329B1 (en) | 1994-09-12 |
Family
ID=19321169
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910017974A KR940008329B1 (en) | 1991-10-12 | 1991-10-12 | Semiconductor package using inter connect lead and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR940008329B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104591078B (en) * | 2013-10-31 | 2016-08-10 | 无锡华润安盛科技有限公司 | What a kind of MEMS sensor dipped in adhesive dispenser and application thereof dips in gluing method |
-
1991
- 1991-10-12 KR KR1019910017974A patent/KR940008329B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR940008329B1 (en) | 1994-09-12 |
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E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20040820 Year of fee payment: 11 |
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LAPS | Lapse due to unpaid annual fee |