KR930015358A - PLL circuit - Google Patents
PLL circuit Download PDFInfo
- Publication number
- KR930015358A KR930015358A KR1019910022846A KR910022846A KR930015358A KR 930015358 A KR930015358 A KR 930015358A KR 1019910022846 A KR1019910022846 A KR 1019910022846A KR 910022846 A KR910022846 A KR 910022846A KR 930015358 A KR930015358 A KR 930015358A
- Authority
- KR
- South Korea
- Prior art keywords
- output
- voltage controlled
- controlled oscillator
- signal
- level
- Prior art date
Links
- 230000010355 oscillation Effects 0.000 claims abstract 2
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
광대역의 입력주파수에 대하여 록킹 가능하도록한 PLL회로에 관한 것으로, 인가되는 입력주파수를 록킹시키기 위한 PLL회로에 있어서, 상기 입력주파수를 포함한 인가신호들을 비교하기 위한 위상 비교부, 상기 위상비교된 신호를 DC레벨로 만들기 위한 로우패스필터부, 상기 DC레벨에 따라 발진주파수를 발생하도록 다수의 전압제어발진기로된 전압제어발진기군, 상기 DC레벨을 감지해서 상기 전압 제어발진기군중 정상동작중인 전압제어발진기의 출력신호를 출력단으로 내보내고 상기 출력이 상기 위상비교기의 인가신호중 하나로 귀환되도록 하는 선택제어부로 구성된다. 기존의 PLL방식과는 달리 의도된 입력기준주파수에 관계없이 광대역의 록킹범위를 갖게되며, 특히 비디오신호의 디지탈신호 처리시 넓은 범위의 멀티싱크 수평주파수에 대하여 라인록킹된 출력주파수를 안정되게 얻을 수 있는 효과가 있다.A PLL circuit for locking to an input frequency of a wide band, comprising: a phase comparator for comparing applied signals including the input frequency; A low pass filter unit for making a DC level, a voltage controlled oscillator group having a plurality of voltage controlled oscillators to generate an oscillation frequency according to the DC level, and a voltage controlled oscillator of the voltage controlled oscillator which is normally operating And a selection control unit which outputs an output signal to an output terminal and returns the output to one of the application signals of the phase comparator. Unlike the conventional PLL method, it has a wide range of locking range regardless of the intended input reference frequency, and especially when processing digital signals of video signals, the line-locked output frequency can be stably obtained for a wide range of multi-sync horizontal frequencies. It has an effect.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2도는 본 발명의 1실시예에 따른 광대역의 입력주파수에 대하여 록킹(Locking) 가능한 PLL회로도.2 is a PLL circuit diagram capable of locking a wideband input frequency according to an embodiment of the present invention.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910022846A KR960009972B1 (en) | 1991-12-13 | 1991-12-13 | Phase locked loop circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910022846A KR960009972B1 (en) | 1991-12-13 | 1991-12-13 | Phase locked loop circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930015358A true KR930015358A (en) | 1993-07-24 |
KR960009972B1 KR960009972B1 (en) | 1996-07-25 |
Family
ID=19324726
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910022846A KR960009972B1 (en) | 1991-12-13 | 1991-12-13 | Phase locked loop circuit |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR960009972B1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100810501B1 (en) | 2005-12-08 | 2008-03-07 | 한국전자통신연구원 | Wide-Band Multi-Mode Frequency Composer and Variable Frequency Divider |
DE602008004438D1 (en) | 2008-04-09 | 2011-02-24 | Hyundai Motor Co Ltd | Passenger seat device for motor vehicles |
-
1991
- 1991-12-13 KR KR1019910022846A patent/KR960009972B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR960009972B1 (en) | 1996-07-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4205272A (en) | Phase-locked loop circuit for use in synthesizer tuner and synthesizer tuner incorporating same | |
KR950022154A (en) | Clock signal generation circuit | |
KR970019094A (en) | A HORIZONTAL OSCILLATOR | |
KR950026124A (en) | PLL circuit with reduced lock time | |
KR940023208A (en) | Clock detection and phase-locked loop device for digital audio equipment for high definition television | |
US4797637A (en) | PLL frequency synthesizer | |
EP0378190A3 (en) | Digital phase locked loop | |
KR930015358A (en) | PLL circuit | |
KR890006059A (en) | TV receiver | |
CA2192881A1 (en) | PLL Circuit and Noise Reduction Means for PLL Circuit | |
KR920001314A (en) | Wide operating range automatic device for changing the horizontal deflection frequency of multi-sync monitor | |
KR970078025A (en) | PLL EL that improves locking speed | |
JPH1070457A (en) | Pll circuit | |
KR950007297A (en) | Phase locked loop and how it works | |
JPH06291644A (en) | Pll circuit | |
KR0123775B1 (en) | Pll circuit | |
KR910008999Y1 (en) | Mode distinctive circuit of pll | |
KR960009623A (en) | Phase-locked loop frequency synthesizer circuit | |
KR100222075B1 (en) | Pll frequency synthesizer with fastlock time characteristics | |
JPH0529933A (en) | Phase locked loop oscillator | |
JP2745060B2 (en) | PLL frequency synthesizer | |
KR960006943B1 (en) | Digital pll | |
KR0148180B1 (en) | Phase detector by clamp circuit | |
JP2713988B2 (en) | Horizontal AFC circuit | |
KR970055567A (en) | Phase locked loop circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20040629 Year of fee payment: 9 |
|
LAPS | Lapse due to unpaid annual fee |