KR930009548B1 - Planarizing method of semiconductor device using doping process - Google Patents
Planarizing method of semiconductor device using doping process Download PDFInfo
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- KR930009548B1 KR930009548B1 KR1019900018052A KR900018052A KR930009548B1 KR 930009548 B1 KR930009548 B1 KR 930009548B1 KR 1019900018052 A KR1019900018052 A KR 1019900018052A KR 900018052 A KR900018052 A KR 900018052A KR 930009548 B1 KR930009548 B1 KR 930009548B1
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- doping
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- insulating film
- photosensitive material
- planarization
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000004020 conductor Substances 0.000 claims abstract description 27
- 239000000463 material Substances 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims description 26
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 12
- 229910052698 phosphorus Inorganic materials 0.000 claims description 12
- 239000011574 phosphorus Substances 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 claims description 10
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 claims description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 11
- 239000012528 membrane Substances 0.000 description 5
- -1 silicon ions Chemical class 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
제 1 도 내지 제 3 도는 본 발명의 도우핑을 이용한 반도체 장치의 평탄화방법을 설명하기 위한 도면이다.1 to 3 are diagrams for explaining a planarization method of a semiconductor device using the doping of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2 : 절연막1 substrate 2 insulating film
31, 32, 41, 42 : 도체층 5 : 층간절연막31, 32, 41, 42: conductor layer 5: interlayer insulating film
6 : 감광성 물질6: photosensitive material
본 발명은 도우핑을 이용한 반도체 장치의 부분 평탄화방법에 관한 것으로서, 부분적으로 평탄화정도를 다르게 하고자 하는 경우 인위적으로 도우핑농도를 달리하여 불순물을 도우핑 함으로써 필요한 부분의 평탄화정도를 조절할 수 있는 도우핑을 이용한 반도체 장치의 부분 평탄화방법에 관한 것이다.The present invention relates to a partial planarization method of a semiconductor device using doping, and in order to partially vary the degree of planarization, a doping that can adjust the degree of planarization of a necessary portion by doping impurities by artificially varying the doping concentration. The partial planarization method of the semiconductor device using the present invention is related.
종래의 반도체 장치를 제조함에 있어서, 부분적으로는 평탄화를 실시할 수 없었고, 전면 평탄화를 실시하는 방법 밖에는 없었다.In manufacturing a conventional semiconductor device, planarization can be partially performed, and only a method of performing front planarization is available.
그러므로, 종래에는 플로우(Flow) 가능한 절연체를 도포하는데 있어서 부분적으로 절연막의 농도 변화나 온도 변화 또는 도포되는 절연막의 양을 조절할 수가 없기 때문에, 제 1 도에 도시되어 있는 바와같이 단차가 높은 A부분이나 단차가 낮은 B부분 또는 단차를 형성하는 부분의 간격(W1), (W2)에 관계없이 같은 절연막이 분위기에서 같은 시간동안 플로우되어 전체적으로 똑같이 도포되므로 토폴로지(Topology) 단차가 서로 다른 영역 특히, 단차가 높은 A부분에서는 B부분에서 보다 평탄화가 제대로 이루어지지 않게 된다.Therefore, in the conventional application of a flowable insulator, it is not possible to partially adjust the concentration change of the insulating film, the temperature change, or the amount of the insulating film to be applied. Therefore, as shown in FIG. Regardless of the intervals W1 and W2 of the low stepped portion or the portion forming the stepped, the same insulating film flows in the atmosphere for the same time and is applied in the same way, so that the topologies are different from each other. In the high A part, the flattening is not performed properly in the B part.
따라서, 후속공정이 계속 이어지는 경우에 사진식각 공정시 어려움이 따르게 되고, 그 위에 다른 층이 형성되는 경우에 기울어짐으로 인하여 여러가지 문제점이 발생하게 된다.Therefore, when the subsequent process continues, the photolithography process is difficult, and when the other layer is formed thereon, various problems occur due to the inclination.
본 발명은 상기한 종래 기술의 문제점을 해결하기 위한 것으로서, 본 발명은 평탄화가 필요한 부분에 불순물을 도우핑을 하여 평탄화정도를 달리하여 줌으로써 평탄화를 도체층의 단차 및 도체층간의 간격을 고려하여 선택적으로 실시할 수 있는 도우핑을 이용한 반도체 장치의 부분 평탄화방법을 제공하는데 그 목적이 있다.The present invention is to solve the above problems of the prior art, the present invention is to select the planarization in consideration of the step of the conductor layer and the gap between the conductor layer by varying the degree of planarization by doping the impurity to the portion that needs to be planarized. SUMMARY OF THE INVENTION An object of the present invention is to provide a method of partially planarizing a semiconductor device using doping, which can be carried out.
상기 목적을 달성하기 위한 본 발명은, 기판상에 절연막을 형성하고, 그 위에는 높은 단차를 갖으며 소정 간격을 두고 형성되어 있는 도체층과 낮은 단차를 갖으며 소정 간격을 두고 도체층을 형성하며, 그 위에는 층간 절연막을 형성하는 공정을 포함하는 반도체 장치의 평탄화방법에 있어서, 기판전면에 걸쳐 감광성 물질을 도포한 다음 단차가 높은 도체층부분에서 상기 감광성 물질을 사진식각하여 제거하고, 단차가 낮은 도체층부분에서는 감광성 물질을 그대로 남겨두는 공정과, 평탄화정도에 따라 불순물의 농도를 달리하여 기판전면에 걸쳐 도우핑하는 공정과, 상기 감광성 물질을 제거한 다음 열처리공정을 실시하여 불순물이 도우핑된 단차가 높은 도체층 영역에서 단차가 낮은 도체층영역보다 평탄화를 더 시키는 공정을 포함하는 도우핑을 이용한 부분 반도체 장치의 부분 평탄화방법을 제공하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides an insulating film on a substrate, and a conductor layer having a high step and a predetermined step thereon and a conductor layer formed at a predetermined interval thereon and a conductor layer having a predetermined step, In the planarization method of a semiconductor device comprising the step of forming an interlayer insulating film thereon, by applying a photosensitive material over the entire surface of the substrate, the photosensitive material is removed by photo-etching in the portion of the high conductor layer, the conductor having a low step In the layer part, the step of leaving the photosensitive material as it is, the step of doping over the entire surface of the substrate by varying the concentration of impurities according to the degree of planarization, the step of removing the photosensitive material and performing a heat treatment process to remove the stepped dopant In the high conductor layer region, doping may be performed including a step of planarizing more than the low conductor layer region. Yonghan part characterized in that it provides partial planarization method for a semiconductor device.
이하 첨부 도면에 의거하여 본 발명의 실시예를 상세하게 설명한다.EMBODIMENT OF THE INVENTION Hereinafter, the Example of this invention is described in detail based on an accompanying drawing.
제 2 도 내지 제 3 도는 본 발명의 반도체 장치의 평탄화방법을 설명하기 위한 도면이다.2 to 3 are diagrams for explaining the planarization method of the semiconductor device of the present invention.
제 2 도를 참조하면, 기판(1)상에 절연막(2)이 형성되어 있고, 그 위에는 반도체 장치의 전극 등이 되는 단자(L1)를 갖는 도체층(31), (32) 및 단차(L2)를 갖는 도체층(41), (42)이 형성되어 있다.Referring to FIG. 2, an insulating film 2 is formed on a substrate 1, on which conductor layers 31, 32, and steps L2 having terminals L1 serving as electrodes of a semiconductor device, etc. are formed. The conductor layers 41 and 42 which have () are formed.
상기한 반도체 장치의 단면을 살펴보면 수직구조가 일정하지 않아 A부분에서의 도체층(31), (32)의 단차(L1)와 B부분에서의 도체층(41), (42)의 단차(L2)가 다르며, 또한 A부분에서의 단자(L1)를 형성하는 도체층(31)과 도체층(32) 사이의 간격(W1)과 B부분에서의 단차(L2)를 형성하는 도체층(41)과 도체층(42) 사이의 간격(W2)이 서로 다르기 때문에 A부분에서와 B부분에서의 층간 절연막(5)이 도포되어 있는 상태는 다르게 나타난다.Looking at the cross-section of the semiconductor device described above, the vertical structure is not constant, so the step L1 of the conductor layers 31 and 32 in the A part and the step L2 of the conductor layers 41 and 42 in the B part are ) Is different, and the conductor layer 31 forming the gap W1 between the conductor layer 31 and the conductor layer 32 forming the terminal L1 in the A portion and the conductor layer 32 and the step L2 in the B portion. Since the intervals W2 between the and conductor layers 42 are different from each other, the state in which the interlayer insulating film 5 is applied in the A portion and the B portion appears different.
층간 절연막(5)으로 PSG(Phospho Silicate Glass)막 또는 보론(B)이 함유된 BPSG(Boro Phospho Silicate Glass)막이 사용되어진다. 그러므로, 제 2 도에서 보는 바와같이 B부분에서보다 A부분에서의 절연막(5)이 평탄화정도가 더 필요하게 된다.As the interlayer insulating film 5, a PSG (Phospho Silicate Glass) film or a BPSG (Boro Phospho Silicate Glass) film containing boron (B) is used. Therefore, as shown in FIG. 2, the degree of planarization of the insulating film 5 in the A portion is more necessary than in the B portion.
이를 위해서 기판전면에 걸쳐 감광성 물질(6)을 도포한 다음 평탄화가 더 필요한 A부분 즉, 후속공정시 도전체층이 더 형성될 부분에서는 상기 감광성 물질을 사진식각하여 제거하고, 평탄화가 덜필요한 B부분 즉, 콘택부가 형성될 부분으로서 스텝커버리지를 개선할 부분에서는 감광성 물질(6)을 그대로 남겨둔다.To this end, after the photosensitive material 6 is applied over the entire surface of the substrate, the portion A which needs to be further planarized, that is, the portion where the conductor layer will be further formed in a subsequent process, is photo-etched and removed, and the portion B which requires less planarization That is, the photosensitive material 6 is left as it is in the part where the contact portion is to be improved and the step coverage is to be improved.
그 다음, 기판전면에 걸쳐 불순물을 도우핑하게 되는데, 감광성 물질(6)이 남아있는 B부분에서는 감광성 물질(6)에 의해 불순물이 도우핑되지 않고, 감광성 물질(6)이 제거된 A부분에서는 불순물이 도우핑되어 제 2 도에 도시되어 있는 바와같이 된다. 부호 7은 불순물이 도우핑된 영역을 나타내는 것으로, 이때 주입되는 불순물은 보론(B)이나 인(P)이다.Then, impurities are doped over the entire surface of the substrate. In the portion B where the photosensitive material 6 remains, the impurities are not doped by the photosensitive material 6, and in the portion A where the photosensitive material 6 is removed. Impurities are doped to form as shown in FIG. Reference numeral 7 denotes a region doped with impurities, wherein the impurities to be injected are boron (B) or phosphorus (P).
제 3 도를 참조하면, 상기 감광성 물질(6)을 제거한 다음 평탄화를 위하여 열처리공정을 실시하면, A부분에서는 도우핑된 불순물에 의해 B부분에서 보다 층간 절연막(5)이 더 평탄화되게 된다.Referring to FIG. 3, when the photosensitive material 6 is removed and a heat treatment process is performed to planarize, the interlayer insulating film 5 is planarized more in the portion B due to the doped impurities in the portion A. FIG.
상기에서 층간 절연막(5)으로 사용되는 PSG 막과 BPSG 막의 특성을 살펴본다.The characteristics of the PSG film and the BPSG film used as the interlayer insulating film 5 will be described.
1) PSG 막1) PSG membrane
PSG 막은 다음과 같은 반응식을 갖는다.The PSG membrane has the following reaction formula.
SiH4+O2→ SiO2+2H2 SiH 4 + O 2 → SiO 2 + 2H 2
2PH3+4O2→ P2O5+3H2O2PH 3 + 4O 2 → P 2 O 5 + 3H 2 O
즉, SiO2에 P2O5가 포함되는 막이 형성되는 것이다.In other words, a film containing P 2 O 5 is formed in SiO 2 .
상기식에서 살펴보면, PSG 막의 열팽창계수(Thermal Expansion Coefficient)는 P2O5의 함유량의 함수이므로 하부에 놓여 있는 실리콘 기판과 열적으로 매칭되도록 조절할 수 있다.Looking at the above equation, since the thermal expansion coefficient of the PSG film is a function of the content of P 2 O 5 can be adjusted so as to thermally match the underlying silicon substrate.
PSG 막의 에칭율도 P2O5의 함유량에 따라 증가하는데, 이는 에칭할 때 유용하게 응용될 수 있고, 또한 실리콘 이온(Si)을 잡아두는데 효과가 있으며, 보통 최종공정에서 스크래치(Scratch)를 방지하기 위하여 또는 알칼리 이온의 침투를 막기 위하여 코팅하기도 한다.The etching rate of the PSG film also increases with the content of P 2 O 5 , which can be usefully applied when etching, and also effective in trapping silicon ions (Si), and usually prevents scratches in the final process. It may also be coated in order to prevent the penetration of alkali ions.
또한, PSG 막은 알루미늄막이 인접해 있는 경우 알루미늄을 부식시키기도 하는데, 저온공정에서는 수분에 의한 문제가 있으나, 고온공정에서는 별문제가 없다.In addition, the PSG film may corrode aluminum when the aluminum film is adjacent, but there is a problem due to moisture in the low temperature process, but no problem in the high temperature process.
리플로우를 증가시키기 위해서는 인(P)의 농도가 높은 PSG 막이 좋으므로 리플로우시킬 때는 인의 농도를 증가시켰다가 리플로우를 시킨후에는 어닐링을 하여 인을 제거하여 줌으로써 알루미늄의 부식을 방지할 수 있다.In order to increase the reflow, a PSG film having a high concentration of phosphorus (P) is preferable. Therefore, when reflowing, the concentration of phosphorus is increased, and after reflowing, annealing is performed to remove phosphorus to prevent corrosion of aluminum. .
2) BPSG 막2) BPSG membrane
층간 절연막으로 널리 사용되어온 8-10% P2O5농도가 상기한 PSG 막은 순수한 산화막(SiO2)에 비하여 리플로우 온도가 낮아 1000 내지 1100℃에서도 단차 피복성(Step coverage)이 좋다. 그러나 더 낮은 온도에서 리플로우 시키기 위해서는 인의 농도를 높혀야 하는데, 인의 농도를 높히게 되면 흡수성이 커지게 되고, 이로 인하여 알루미늄이 부식되거나 감과성 물질의 접착성이 저하된다.The PSG film having a concentration of 8-10% P 2 O 5, which has been widely used as an interlayer insulating film, has a low reflow temperature compared to pure oxide film (SiO 2 ) and thus has good step coverage even at 1000 to 1100 ° C. However, in order to reflow at a lower temperature, the concentration of phosphorus must be increased. Increasing the concentration of phosphorus increases the absorbency, which leads to corrosion of aluminum and deterioration of adhesion of the susceptible material.
그러나, 보론이 함유된 BPSG 막은 인의 농도를 낮추는 대신에 보론을 첨가함으로써 리플로우 온도를 낮출 수 있으므로 BPSG 막은 인의 농도가 낮음에 따라 내습성 및 내부식성이 좋다.However, since the BPSG membrane containing boron can lower the reflow temperature by adding boron instead of lowering the concentration of phosphorus, the BPSG membrane has good moisture resistance and corrosion resistance as the concentration of phosphorus is low.
상기한 층간 절연막에 인이나 보론이온을 도우핑시키면 보론이온의 경우는 산소이온이 증가하고, 인의 경우는 결핍이 일어나 구조가 약해지고 따라서 용융점(Melting point)가 낮아지게 된다.Doping phosphorus or boron ions to the interlayer insulating film increases oxygen ions in the case of boron ions, and deficiency occurs in the case of phosphorus, resulting in a weaker structure and thus a lower melting point.
그러므로, 평탄화용 절연막으로 PSG 막이나 BPSG 막을 사용하고, 인이나 보론이온을 도우핑시킬 때 도우핑농도를 조절함으로써 필요한 부분에서의 평탄화정도를 후속공정을 고려하여 선택할 수 있으며, 이에 따라 후속공정을 용이하게 실시할 수 있다.Therefore, by using a PSG film or a BPSG film as a planarization insulating film and adjusting the doping concentration when doping phosphorus or boron ions, the degree of planarization at a necessary part can be selected in consideration of the subsequent process. It can be implemented easily.
상기한 바와같은 본 발명에 따르면, 단차가 다르거나 단차를 형성하는 층사이의 간격이 다른 경우의 평탄화 공정시, 후속공정을 고려하여 필요에 따라 도우핑농도를 조절함에 따라 평탄화정도를 선택할 수 있는 이점이 있으며, 이로 인하여 후속공정을 용이하게 실시할 수 있는 이점이 있다.According to the present invention as described above, in the planarization process when the step is different or the gap between the layers forming the step is different, the degree of planarization can be selected by adjusting the doping concentration as necessary in consideration of the subsequent process. There is an advantage, and thus there is an advantage that can be easily carried out subsequent processes.
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