KR930008989A - Multi-layer resist process using selective SOG coating area - Google Patents

Multi-layer resist process using selective SOG coating area Download PDF

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Publication number
KR930008989A
KR930008989A KR1019910017943A KR910017943A KR930008989A KR 930008989 A KR930008989 A KR 930008989A KR 1019910017943 A KR1019910017943 A KR 1019910017943A KR 910017943 A KR910017943 A KR 910017943A KR 930008989 A KR930008989 A KR 930008989A
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KR
South Korea
Prior art keywords
film
sog
layer
photoresist film
etching
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KR1019910017943A
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Korean (ko)
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허훈
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문정환
금성 일렉트론 주식회사
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Priority to KR1019910017943A priority Critical patent/KR930008989A/en
Publication of KR930008989A publication Critical patent/KR930008989A/en

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Abstract

본 발명은 선택적 SOG 도포영역을 이용한 다층레지스트 공정에 관한 것으로, 특히 단차가 심한 기판에서 감강막의 형성에 적당하도록 한 다층 레지스트 공정에 관한 것이다. 이를 위하여 본 발명에서는, 다층 레지스트 공정에서, 실리콘 기판의 기판단차를 평탄화시켜주기 위해서 후막 상태로 하층감광막을 도포하고, 건식식각시 에칭 선택비를 고려하여 질소(N2) 분위기에서 UV 경화(Ultra Violit Cure) 및 베이크(Bake)하는 단계(a)와, 상층 감광막의 임계치수 조절 및 공정조건의 원활한 진행을 위해서 중간층막으로서 상층막과 감도차를 나타내는 폴리마이드(Polymide) 또는 PMMA, 음성(negative) 감광막등을 도포하는 단계(b)와, 상기 중간층위에 상층 양성(Positive) 감광막을 박막 상태로 도포하는 단계(b)와, 레티클을 이용하여 노광을 실시하고 현상을 통해 상층 감광막의 미세 형상을 얻는 단계(d)와, 현상된 상층감광막에 SOG 막을 도포하여 현상된 상층감광막 영역내로 SOG를 채운후 SOG 막의 산화물 에치 백 공정을 실시하는 단계(e)와, 이처럼 형성된 SOG 영역을 이용해서 산소(O2)RIE 건식식각을 통해 상층부 감광막을 식각하는 단계(f)와, 중간층 및 평탄화를 위해 사용되었던 하층 감광막을 동일하게 건식식각을 실시하는 단계(g)를 포함하여 이루어지는 선택적 SOG 도포 영역을 이용한 다층레지스트 공정.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layer resist process using selective SOG coating areas, and more particularly to a multi-layer resist process suited for the formation of a film on a highly stepped substrate. To this end, in the present invention, in the multilayer resist process, in order to planarize the substrate step of the silicon substrate, the lower layer photosensitive film is applied in a thick film state, and UV curing (Ultra) in a nitrogen (N 2 ) atmosphere in consideration of the etching selectivity during dry etching. Step (a) of Violit Cure and Bake, and polyamide or PMMA, which shows the difference in sensitivity from the upper layer as the intermediate layer for controlling the critical dimension of the upper photoresist layer and the smooth progress of the process conditions, is negative. ) (B) applying a photoresist film, etc., (b) applying a positive photoresist film on the intermediate layer in a thin film state, and performing exposure using a reticle and developing a fine shape of the upper photoresist film through development. (D) obtaining step (d), applying a SOG film to the developed upper photoresist film, filling the SOG into the developed upper photoresist area, and then performing an oxide etch back process of the SOG film; Using the formed SOG regions oxygen (O 2) comprises the step of performing RIE dry and step (f) of etching the upper photoresist layer through etching, dry etching in the same manner a lower layer photosensitive film which was used for the intermediate layer, and planarizing (g) The multilayer resist process using the selective SOG coating area | region made.

Description

선택적 SOG 도포 영역을 이용한 다층 레지스트 공정Multi-layer resist process using selective SOG coating area

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 2도는 본 발명의 선택적 SOG 도포 영역을 이용한 다층 레지스트 공정도.2 is a multilayer resist process diagram using the selective SOG coating area of the present invention.

Claims (1)

다층 레지스트 공정에 있어서, 실리콘 기판의 기판단차를 평탄화시켜주기 위해서 후막 상태로 하층감광막을 도포하고, 건식식각시 에칭 선택비를 고려하여 질소(N2) 분위기에서 UV 강화(Ultra Violit Cure) 및 베이크(Bake) 하는 단계(a)와, 상층 감광막의 임계치수 조절 및 공정조건의 원활한 진행을 위해서 중간층막으로서 상층막과 감도차를 나타내는 폴리마이드(Polymide) 또는 PMMA, 음성(negative) 감광막등을 도포하는 단계(b)와, 상기 중간층위에 상층 양성(Positive) 감광막을 박막 상태로 도포하는 단계(b)와, 레티클을 이용하여 노광을 실시하고 현상을 통해 상층 감광막의 미세 형상을 얻는 단계(d)와, 현상된 상층감광막에 SOG 막을 도포하여 현상된 상층감광막 영역내로 SOG를 채운후 SOG 막의 산화물 에치 백 공정을 실시하는 단계(e)와, 이처럼 형성된 SOG 영역을 이용해서 산소(O2) RIE 건식식각을 통해 상층부 감광막을 식각하는 단계(f)와, 중간층 및 평탄화를 위해 사용되었던 하층 감광막을 동일하게 건식식각을 실시하는 단계(g)를 포함하여 이루어지는 선택적 SOG 도포 영역을 이용한 다층레지스트 공정.In the multilayer resist process, in order to planarize the substrate step of the silicon substrate, the lower layer photoresist film is applied in a thick film state, and UV enhanced and bake in a nitrogen (N 2 ) atmosphere in consideration of the etching selectivity during dry etching. (B) to apply a polymide or PMMA, a negative photosensitive film having a sensitivity difference with the upper film as an intermediate layer for the step (a) of the baking and the smooth adjustment of the critical dimension of the upper photoresist film and the process conditions. Step (b), applying a positive photoresist film in a thin film state on the intermediate layer (b), and performing exposure using a reticle and obtaining a fine shape of the upper photoresist film through development (d). And (e) applying an SOG film to the developed upper photoresist film to fill the SOG into the developed upper photoresist area, and then performing an oxide etch back process of the SOG film. Selective SOG comprising the step (f) of etching the upper photoresist film through oxygen (O 2 ) RIE dry etching and the same step of dry etching the lower photoresist film used for planarization (g). Multi-layer resist process using coating area. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019910017943A 1991-10-12 1991-10-12 Multi-layer resist process using selective SOG coating area KR930008989A (en)

Priority Applications (1)

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KR1019910017943A KR930008989A (en) 1991-10-12 1991-10-12 Multi-layer resist process using selective SOG coating area

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KR1019910017943A KR930008989A (en) 1991-10-12 1991-10-12 Multi-layer resist process using selective SOG coating area

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100907889B1 (en) * 2007-11-29 2009-07-15 주식회사 동부하이텍 How to form a mask pattern

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100907889B1 (en) * 2007-11-29 2009-07-15 주식회사 동부하이텍 How to form a mask pattern

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