KR920013998A - Data relay control signal relay circuit - Google Patents

Data relay control signal relay circuit Download PDF

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Publication number
KR920013998A
KR920013998A KR1019900022483A KR900022483A KR920013998A KR 920013998 A KR920013998 A KR 920013998A KR 1019900022483 A KR1019900022483 A KR 1019900022483A KR 900022483 A KR900022483 A KR 900022483A KR 920013998 A KR920013998 A KR 920013998A
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KR
South Korea
Prior art keywords
operation state
control signal
relay
transfer means
controlling
Prior art date
Application number
KR1019900022483A
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Korean (ko)
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KR0176446B1 (en
Inventor
전영진
Original Assignee
정용문
삼성전자 주식회사
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Priority to KR1019900022483A priority Critical patent/KR0176446B1/en
Publication of KR920013998A publication Critical patent/KR920013998A/en
Application granted granted Critical
Publication of KR0176446B1 publication Critical patent/KR0176446B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)
  • Bus Control (AREA)

Abstract

내용 없음No content

Description

데이터중계 제어신호 중계회로Data relay control signal relay circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 데이터 중계제어신호 중계회로가 적용된 FDDI-LAN시스템도이다. 제2도는 본 발명의 실시예의 데이터중계제어신호 중계회로의 회로도이다. 제3도는 제2도의 입출력파형도이다.1 is an FDDI-LAN system diagram to which the data relay control signal relay circuit of the present invention is applied. 2 is a circuit diagram of a data relay control signal relay circuit of an embodiment of the present invention. 3 is an input / output waveform diagram of FIG.

Claims (2)

로컬메모리를 제어하고 정보중계작동을 제어처리하기 위한 노드 프로세서와, 로컬메모리와 정보를 주고 받기 위한 버퍼메모리를 제어하는 RBC를 구비한 FDDI-LAN시스템에 있어서; 상기 메모리억세스 명령에 따른 RBC의 작동상태를 감지하여 상기 노드프로세서쪽으로 전달하기 위한 작동 상태전달수단을 포함함을 특징으로 하는 데이타중계제어신호중계회로.A FDDI-LAN system having a node processor for controlling a local memory and controlling information relay operation, and an RBC for controlling a buffer memory for exchanging information with the local memory; And an operation state transfer means for detecting an operation state of the RBC according to the memory access command and transferring the operation state to the node processor. 제1항에 있어서, 억세스명령전달수단 및 작동상태전달수단이 논리 소자들로 이루어짐을 특징으로 하는 데이타중계신호중계회로.The data relay signal relay circuit as claimed in claim 1, wherein the access command transfer means and the operation state transfer means are made of logic elements. ※ 참고사항 : 최초출원내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900022483A 1990-12-29 1990-12-29 Junction circuit of data junction control signal KR0176446B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900022483A KR0176446B1 (en) 1990-12-29 1990-12-29 Junction circuit of data junction control signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900022483A KR0176446B1 (en) 1990-12-29 1990-12-29 Junction circuit of data junction control signal

Publications (2)

Publication Number Publication Date
KR920013998A true KR920013998A (en) 1992-07-30
KR0176446B1 KR0176446B1 (en) 1999-05-15

Family

ID=19308982

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900022483A KR0176446B1 (en) 1990-12-29 1990-12-29 Junction circuit of data junction control signal

Country Status (1)

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KR (1) KR0176446B1 (en)

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Publication number Publication date
KR0176446B1 (en) 1999-05-15

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