KR910019047A - Cache memory built-in semiconductor memory - Google Patents

Cache memory built-in semiconductor memory Download PDF

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Publication number
KR910019047A
KR910019047A KR1019910005672A KR910005672A KR910019047A KR 910019047 A KR910019047 A KR 910019047A KR 1019910005672 A KR1019910005672 A KR 1019910005672A KR 910005672 A KR910005672 A KR 910005672A KR 910019047 A KR910019047 A KR 910019047A
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KR
South Korea
Prior art keywords
open
cache
memory
response
accessed
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KR1019910005672A
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Korean (ko)
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KR940008140B1 (en
Inventor
요시오 마쓰다
가즈야스 후지시마
히데도 히다가
미끼오 아사구라
Original Assignee
시기 모리야
미쓰비시뎅끼가부시끼가이샤
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Publication of KR910019047A publication Critical patent/KR910019047A/en
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Publication of KR940008140B1 publication Critical patent/KR940008140B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

내용 없음No content

Description

캐쉬메모리 내장반도체 기억장치Cache memory built-in semiconductor memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 이 발명의 한 실시예에 의한 캐쉬 DRAM의 구성을 표시하는 블럭도.1 is a block diagram showing the configuration of a cache DRAM according to an embodiment of the present invention.

Claims (1)

1칩상에 형성되는 캐쉬메모리 내장반도체 기억장치이고, 다중화된 열어드레스 신호 및 행어드레스 신호를 받는 어드레스 수신수단, 상기 행어드레스 신호 및 상이 열어드레스 신호에 응답하여 엑세스되는 다이내믹형 메모리 수단, 및 상기 열어드레스 신호의 적어도 일부에 응답하여 엑세스되는 스태틱형메모리 수단을 구비하고, 캐쉬히트 및 캐쉬미스 판정시에 상기 어드레스 수신수단으로부터의 상기 열어드레스 신호의 적어도 일부에 응답하여 상기 스태틱형 메모리 수단이 엑세스되어, 캐쉬미스에는 상기 어드레스 수신수단으로부터의 상기 헹어드레스 신호 및 상기 열어드레스 신호에 응답하여 상기 다이내믹형 메모리 수단이 다시금 엑세스되는 캐쉬메모리 내장반도체 기억장치.A semiconductor memory device with a built-in cache memory formed on one chip, the address receiving means receiving multiplexed open-dress signals and row address signals, the dynamic memory means in which the row address signals and the phase are accessed in response to the open-dress signal, and the open And static memory means accessed in response to at least a portion of the dress signal, wherein the static memory means is accessed in response to at least a portion of the open-dress signal from the address receiving means in determining cache hits and cache misses. And a cache memory in which the dynamic memory means is again accessed in response to the rinse dress signal and the open dress signal from the address receiving means. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910005672A 1990-04-13 1991-04-09 Semiconductor memory device having cash memory KR940008140B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP9878290A JP2862948B2 (en) 1990-04-13 1990-04-13 Semiconductor storage device
JP2-98782 1990-04-13

Publications (2)

Publication Number Publication Date
KR910019047A true KR910019047A (en) 1991-11-30
KR940008140B1 KR940008140B1 (en) 1994-09-03

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Application Number Title Priority Date Filing Date
KR1019910005672A KR940008140B1 (en) 1990-04-13 1991-04-09 Semiconductor memory device having cash memory

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US (1) US5509132A (en)
JP (1) JP2862948B2 (en)
KR (1) KR940008140B1 (en)

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Also Published As

Publication number Publication date
JPH03296992A (en) 1991-12-27
US5509132A (en) 1996-04-16
JP2862948B2 (en) 1999-03-03
KR940008140B1 (en) 1994-09-03

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