KR910010625A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR910010625A
KR910010625A KR1019890016957A KR890016957A KR910010625A KR 910010625 A KR910010625 A KR 910010625A KR 1019890016957 A KR1019890016957 A KR 1019890016957A KR 890016957 A KR890016957 A KR 890016957A KR 910010625 A KR910010625 A KR 910010625A
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KR
South Korea
Prior art keywords
semiconductor device
contact hole
chamber
manufacturing
tungsten film
Prior art date
Application number
KR1019890016957A
Other languages
Korean (ko)
Other versions
KR930000309B1 (en
Inventor
김의송
고광옥
박선후
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019890016957A priority Critical patent/KR930000309B1/en
Priority to JP2046027A priority patent/JPH03169010A/en
Priority to GB9013037A priority patent/GB2239661A/en
Priority to DE4018801A priority patent/DE4018801A1/en
Publication of KR910010625A publication Critical patent/KR910010625A/en
Application granted granted Critical
Publication of KR930000309B1 publication Critical patent/KR930000309B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562—Selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

내용 없음No content

Description

반도체 장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 선택적 화학 기상증착법에 의 해 형성된 반도체 장치의 단면도3 is a cross-sectional view of a semiconductor device formed by the selective chemical vapor deposition method of the present invention.

제 4도는 본 발명의 선택적 화학 기상 증착법에 의해 형성된 텅스텐막의 누설전류 특성도이다4 is a leakage current characteristic diagram of a tungsten film formed by the selective chemical vapor deposition method of the present invention.

Claims (4)

집합층(2)이 형성된 반도체 기판(1)상에 절연막(3)을 형성하고, 이 접합층(2)상부에 접촉구를 형성한 후 이 접촉구를 통하여 접합층(2)과 금속배선을 하는 반도체 장치의 제조방법에 있어서, 상기 접촉구의 형성 후, 1차로 텅스텐막(41)을 접촉구에만 선택적으로 화학 기상 증착시키는데 제1공정과, 상기 제1차 텅스텐막(41)상에 2차로 텅스텐막(42)을 선택적으로 화학기상 증척시키는데 제2공정으로 이루어지는 것을 특징으로 하는 반도체 장치의 제도방법An insulating film 3 is formed on the semiconductor substrate 1 on which the assembly layer 2 is formed, a contact hole is formed on the junction layer 2, and then the junction layer 2 and the metal wiring are formed through the contact hole. In the method of manufacturing a semiconductor device, after the formation of the contact hole, the first step of selectively chemically vapor-depositing the tungsten film 41 only on the contact hole and the second process on the first tungsten film 41. A method for drafting a semiconductor device, characterized in that the second process is performed for selectively chemical vapor deposition of the tungsten film (42). 제1항에 있어서, 제1공정은 250℃이하의 저온 상태에서 수행되고 , 제2공정은 350℃이상의 고온상태에서 수행되어지는 것을 특징으로 하는 반도체 장치의 제도 방법The method of drawing a semiconductor device according to claim 1, wherein the first step is performed at a low temperature of 250 ° C or lower, and the second step is performed at a high temperature of 350 ° C or higher. 제1항에 있어서 ,상기 제1공정과 제2공정이 하나의 챔버 내에서 연속적으로 이루어지는 것을 특징으로 하는 반도체 장치의 제도방법The method of claim 1, wherein the first process and the second process are continuously performed in one chamber. 제1항에 있어서, 상기 제1공정이 제1챔버내에서 수행된 후, 상기 제2공정은 제2챔버내에서 대기의 노출없이 연속적으로 이루어지는 것을 특징으로 하는 반도체장치의 제도방법.The method of claim 1, wherein after the first process is performed in the first chamber, the second process is continuously performed in the second chamber without exposing the atmosphere. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임※ Note: The disclosure is based on the initial application.
KR1019890016957A 1989-11-22 1989-11-22 Manufacturing method of semiconductor device KR930000309B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019890016957A KR930000309B1 (en) 1989-11-22 1989-11-22 Manufacturing method of semiconductor device
JP2046027A JPH03169010A (en) 1989-11-22 1990-02-28 Manufacture of semiconductor device
GB9013037A GB2239661A (en) 1989-11-22 1990-06-12 Semiconductor devices provided with two metallic films
DE4018801A DE4018801A1 (en) 1989-11-22 1990-06-12 Semiconductor device prodn. - involving two-stage tungsten CVD in contact hole

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890016957A KR930000309B1 (en) 1989-11-22 1989-11-22 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
KR910010625A true KR910010625A (en) 1991-06-29
KR930000309B1 KR930000309B1 (en) 1993-01-15

Family

ID=19291917

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890016957A KR930000309B1 (en) 1989-11-22 1989-11-22 Manufacturing method of semiconductor device

Country Status (4)

Country Link
JP (1) JPH03169010A (en)
KR (1) KR930000309B1 (en)
DE (1) DE4018801A1 (en)
GB (1) GB2239661A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9219281D0 (en) * 1992-09-11 1992-10-28 Inmos Ltd Manufacture of semiconductor devices
GB9219267D0 (en) * 1992-09-11 1992-10-28 Inmos Ltd Manufacture of semiconductor devices
KR960006436B1 (en) * 1992-12-17 1996-05-15 삼성전자주식회사 Manufacturing method of contact plug of semiconductor device
US5489552A (en) * 1994-12-30 1996-02-06 At&T Corp. Multiple layer tungsten deposition process

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4849260A (en) * 1986-06-30 1989-07-18 Nihon Sinku Gijutsu Kabushiki Kaisha Method for selectively depositing metal on a substrate
JPS63149378A (en) * 1986-12-12 1988-06-22 Fujitsu Ltd Vapor growth method
JPS63153273A (en) * 1986-12-16 1988-06-25 Matsushita Electric Ind Co Ltd Method for selective deposition of thin metallic film
DE3818509A1 (en) * 1987-06-01 1988-12-22 Gen Electric METHOD AND DEVICE FOR PRODUCING A LOW-RESISTANT CONTACT WITH ALUMINUM AND ITS ALLOYS THROUGH SELECTIVE DEPOSITION OF TUNGSTEN
EP0305143B1 (en) * 1987-08-24 1993-12-08 Fujitsu Limited Method of selectively forming a conductor layer
JPH0719841B2 (en) * 1987-10-02 1995-03-06 株式会社東芝 Semiconductor device
EP0319214A1 (en) * 1987-12-04 1989-06-07 AT&T Corp. Method for making semiconductor integrated circuits using selective tungsten deposition

Also Published As

Publication number Publication date
JPH03169010A (en) 1991-07-22
GB9013037D0 (en) 1990-08-01
GB2239661A (en) 1991-07-10
DE4018801A1 (en) 1991-05-23
KR930000309B1 (en) 1993-01-15

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