KR910006092B1 - Manufacturing method of semiconductor device using lift-off process - Google Patents

Manufacturing method of semiconductor device using lift-off process Download PDF

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KR910006092B1
KR910006092B1 KR1019880006500A KR880006500A KR910006092B1 KR 910006092 B1 KR910006092 B1 KR 910006092B1 KR 1019880006500 A KR1019880006500 A KR 1019880006500A KR 880006500 A KR880006500 A KR 880006500A KR 910006092 B1 KR910006092 B1 KR 910006092B1
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metal
forming
substrate
wiring
semiconductor device
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KR890017774A (en
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황창구
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삼성전자 주식회사
강진구
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

The semiconductor device using the lift-off method is manufactured by the following steps: (a) forming a contact hole on the semiconductor substrate after forming a mask pattern by using the photoresist; (b) forming a refractory metal and first metal for interconnection line in sequence on the substrate; (c) removing the photoresist pattern; (d) forming a electrode pattern of second metal for interconnection. This method provides an advantage for preventing the short of metal at contact region.

Description

리프트 오프공정을 이용한 반도체장치의 제조방법Manufacturing Method of Semiconductor Device Using Lift-Off Process

제1a-f도는 본 발명에 따른 일실시예의 제조공정도.1a-f is a manufacturing process diagram of an embodiment according to the present invention.

본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 접촉부위(Contact)에서 금속이 끊어짐을 방지하고 단차를 개선시키는 리프트 오프공정을 이용한 반도체장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device using a lift-off process of preventing breakage of metal at a contact portion and improving a step.

반도체소자가 초집적화로 진행됨에 따라 접촉부위(Contact)의 크기는 줄어드는 반면 단차는 일정하게 유지되므로 단차부분에서 금속배선의 끊어짐이나 금속의 이주(electromigration)현상 또는 금속배선간의 단락으로 인한 소자의 신뢰성 저하등 여러문제가 야기되고 있다.As semiconductor devices progress to ultra-integration, the size of contacts decreases while the level of steps remains constant. There are many problems, such as degradation.

또한 다층 배선공정에서는 접촉부위에서의 단차 악화로 인하여 평탄화가 어렵게 되거나 접촉부위에서 구멍(Void)이 형성되는 등의 문제점이 발생했었다.In addition, in the multi-layer wiring process, problems such as difficulty in planarization or formation of voids in contact portions have occurred due to deterioration of the level at the contact portions.

종래에 이런 문제점을 해결하기 위해서 접촉부위 메꿈(Contact Refill) 공정이 개발되어 사용되고 있는데 실리콘 물질상에만 선택적으로 텅스텐이 도포되는 선택적 텅스텐 도포공정, 특정부위에만 선택적으로 에피택셜층이 형성되는 선택적 에피택시공정 그리고 기판전면에 금속을 도포하고 전면적으로 금속을 리플로우(Reflow)시키는 전면 금속 플로우 공정들이 대표적방법이다. 그러나 위의 공정들은 공정이 난이하고 장비의존성이 심하여 다량으로 대규모의 반도체 소자를 제작하는데 있어서는 채택하기 어려운 점이 많았다.In order to solve this problem, a contact refill process has been developed and used in the past. A selective tungsten coating process in which tungsten is selectively applied only on a silicon material, and an selective epitaxy in which an epitaxial layer is selectively formed only on a specific site Processes and front metal flow processes that apply metal to the entire surface of the substrate and reflow the metal over the entire surface are typical methods. However, the above processes were difficult to adopt in manufacturing a large-scale semiconductor device in a large amount due to the difficult process and the equipment dependency.

따라서 본 발명의 목적은 다층배선 반도체장치에서 어떤 크기의 접촉부위에서도 신뢰성 높은 접촉부위를 형성하는 반도체장치의 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device which forms a highly reliable contact portion at any size contact portion in a multilayer wiring semiconductor device.

이하 본 발명을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제1a-f도는 본 발명에 따른 실시예의 제조공정 순서에 따른 수직단면도이다.1a-f are vertical cross-sectional views according to the manufacturing process sequence of the embodiment according to the present invention.

제1a-f도는 모오스 전계효과 트랜지스터에 드레인 및 소오스전극을 형성하는 것을 실시예로 도시하였으나 반도체 장치의 금속과의 접촉영역을 형성하는 어떤 부분에도 이용될 수 있음을 유의하여야 한다.1A-F illustrate the formation of a drain and a source electrode in a MOS field transistor, but it should be noted that it may be used in any portion forming a contact region with a metal of a semiconductor device.

제1a도를 참조하면 반도체기판(10) 상부에 필드산화막(11)으로 둘러쌓인 액티브 영역(a)이 형성되고 상기 액티브 영역(a)의 기판 표면상에 게이트 산화막(12)이 형성되며 게이트 산화막(12)상에 다결정실리콘 게이트전극(13)이 형성되고 게이트 산화막(12)하부의 기판표면에 서로 이격하여 형성된 기판과 반대도전형인 고농도의 소오스 및 드레인영역(14)(15)이 형성되어 있으며 이들은 표준모오스 공정에 의해서 형성된 것이다.Referring to FIG. 1A, an active region a surrounded by the field oxide layer 11 is formed on the semiconductor substrate 10, and a gate oxide layer 12 is formed on the substrate surface of the active region a. A polysilicon gate electrode 13 is formed on (12), and high concentration source and drain regions 14 and 15 are formed on the substrate surface under the gate oxide film 12 and spaced apart from each other. And these are formed by standard Morse processes.

그다음 기판상에 절연막(16)을 도포하고 절연막(16)상에 통상의 사진공정(Photolithography)으로 포토레지스트 패턴(17)을 형성한 후 포토레지스트 패턴(17)을 식각마스크로 하여 노출된 절연막(16)을 에칭하면 제1a도와 같이 소오스 및 드레인 접촉부위에 접속창(18)(19)이 형성된다.Then, the insulating film 16 is coated on the substrate, the photoresist pattern 17 is formed on the insulating film 16 by a normal photolithography, and then the exposed insulating film is formed by using the photoresist pattern 17 as an etching mask. Etching 16 forms connection windows 18 and 19 at the source and drain contacts as shown in FIG. 1A.

그 다음 포토레지스트를 제거하지 않은 상기 기판상에 내화성 금속(RefractoryMetal)(21a)(21b)을 통상의 증착방법으로 증착하고 그 위에 제1배선용금속(23a)(23b)을 증착하면 제1b도와 같이 형성된다.Then, a refractory metal (21a) (21b) is deposited on the substrate without removing the photoresist by a conventional deposition method, and the first wiring metal (23a) (23b) is deposited thereon, as shown in FIG. 1b. Is formed.

이 공정에서 접촉창 영역(18)(19)의 내화성금속(21b)는 이후 고온열처리시 배선금속(23b)의 정션(Junction)쪽으로 확산을 막아서 정션에서의 스파이크(Spike)현상을 방지하게 된다.In this process, the refractory metal 21b of the contact window regions 18 and 19 prevents diffusion of the wiring metal 23b toward the junction of the wiring metal 23b during the high temperature heat treatment, thereby preventing spike phenomenon at the junction.

그다음 통상의 리프트 오프(Lift Off)방법과 마찬가지로 상기 포토레지스트 패턴(17)을 제거하면 포토레지스트(17)와 함께 포토레지스트상의 내화성금속(21a) 및 제1배선용금속(23a)가 제거되어 제1c도와 같이 접촉 부위내에만 금속(21b)(23b)이 남게된다.Then, the photoresist pattern 17 is removed in the same manner as in the conventional lift off method, and together with the photoresist 17, the refractory metal 21a and the first wiring metal 23a on the photoresist are removed to form the first c. Like the tiles, the metals 21b and 23b remain only in the contact portion.

그다음 상기 기판을 약 600℃의 온도로 열처리하면 상기 제1배선금속(23b)이 접촉부위내에서 유동되어 제1d도와 같이 접촉부위가 메꾸어 지게된다.Then, when the substrate is heat-treated at a temperature of about 600 ° C., the first wiring metal 23b flows in the contact portion, thereby filling the contact portion as shown in FIG. 1d.

제1d도에 도시한 바와 같이 제1배선용금속(23b)이 유동되어 접촉부위를 메꾸어주어 이후 형성되는 배선층은 평탄한 기판면에 형성되므로 단차에 의한 모든 문제점이 해결이 가능해진다.As shown in FIG. 1D, the first wiring metal 23b flows to fill the contact portion, and the wiring layer formed thereafter is formed on a flat substrate surface, thereby making it possible to solve all problems due to the step difference.

그다음 실제 배선을 형성하기 위한 제2배선용금속(25)을 증착하고 상기 제2배선용금속(25)상에 통상의 사진공정으로 소오소 및 드레인전극을 형성하기 위한 포토레지스트 패턴(27)을 형성하면 제1e도와 같다.Then, the second wiring metal 25 is formed to form the actual wiring, and the photoresist pattern 27 is formed on the second wiring metal 25 to form the source and drain electrodes in a conventional photographic process. Same as FIG. 1e.

그다음 상기 포토레지스트 패턴(27)을 식각마스크로 노출된 제2배선용금속(25)을 식각한 후 포토레지스터 패턴(27)을 제거하여 소오소 및 드레인전극(28)(29)을 형성하면 제1f도와 같다.Next, after etching the second wiring metal 25 exposing the photoresist pattern 27 as an etching mask, the photoresist pattern 27 is removed to form the source and drain electrodes 28 and 29. Like help

상기에서 제1배선용금속(23b) 및 제2배선용금속(25)은 동일한 금속을 사용할수도 있음은 이 분야의 통상의 지식을 가진자는 쉽게 이해할 것이다.It will be readily understood by those skilled in the art that the first wiring metal 23b and the second wiring metal 25 may use the same metal.

상술한 바와 같이 본 발명은 반도체소자를 제작하고 접촉부위를 형성함에 있어서 리프트 오프공정 및 금속플로우를 사용하여 먼저 접촉부위에 금속물질을 채우고 평탄화된 기판상에 최종의 금속배선을 형성한다.As described above, the present invention uses a lift-off process and a metal flow in fabricating a semiconductor device and forming a contact portion, and then first fills a metal material with the contact portion and forms a final metal wiring on the flattened substrate.

따라서 본 발명은 접촉부위에서의 구멍(Void)을 없애고 단차로 인한 도포된 금속의 금속이주 현상을 방지하며 미세한 접촉부위도 신뢰성 높은 금속배선을 할 수 있다.Therefore, the present invention eliminates voids at the contact portion, prevents metal migration of the coated metal due to the step, and enables highly reliable metal wiring even at the minute contact portion.

또한 본 발명은 접촉부위를 금속으로 메꾸어주므로써 접촉저항의 증가를 방지하며 자기 정합된 접촉부위가 형성된다.In addition, the present invention prevents an increase in contact resistance by filling the contact portion with a metal, and a self-aligned contact portion is formed.

또한 본 발명은 마스크를 추가로 사용하지 않으므로 신뢰성 높은 소자를 복잡한 공정을 거치지 않고 제작할 수 있다.In addition, since the present invention does not additionally use a mask, a highly reliable device can be manufactured without a complicated process.

또한 본 발명은 배선용금속과 소오스, 드레인 및 액티브 접합사이에 내화성금속을 증착시킴으로써 소오스, 드레인 및 액티브 영역의 스파이크를 방지하여 낮은 접합(Shallow Junction)트랜지스터에 사용할 수 있다.In addition, the present invention can be used in a low junction transistor by preventing a spike in the source, drain and active regions by depositing a refractory metal between the wiring metal and the source, drain and active junctions.

Claims (2)

반도체 기판상에 형성된 반도체 소자부분과 금속전극간을 연결하는 접촉부위를 형성하는 공정이 하기공정을 구비하여 하기공정의 연속으로 이루어짐을 특징으로 하는 반도체장치의 제조방법. (a) 상기 기판상에 형성된 반도체 소자부분위에 포토레지스트를 도포하고 접속창 형성을 위한 마스크 패턴을 형성한 후 접속창을 형성하는 공정. (b) 상기 기판상부 전면에 내열성 금속과 제1배선용금속을 순차적으로 형성하는 공정. (c) 상기 포토레지스트 패턴을 제거하는 공정. (d) 상기 기판상에 제2배선용금속을 형성하고 제2배선용금속의 전극패턴을 형성하는 공정.A process for forming a contact portion for connecting a semiconductor element portion and a metal electrode formed on a semiconductor substrate, comprising the following steps, comprising the steps of: (a) applying a photoresist on a portion of the semiconductor element formed on the substrate, forming a mask pattern for forming a connection window, and then forming a connection window. (b) sequentially forming a heat resistant metal and a first wiring metal on the entire upper surface of the substrate. (c) removing the photoresist pattern. (d) forming a second wiring metal on the substrate and forming an electrode pattern of the second wiring metal. 제1항에 있어서, 상기 제1 및 제2배선용금속이 동일한 금속으로 형성함을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the first and second wiring metals are formed of the same metal.
KR1019880006500A 1988-05-31 1988-05-31 Manufacturing method of semiconductor device using lift-off process KR910006092B1 (en)

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