KR910001941A - Morse FET manufacturing method - Google Patents
Morse FET manufacturing method Download PDFInfo
- Publication number
- KR910001941A KR910001941A KR1019890009316A KR890009316A KR910001941A KR 910001941 A KR910001941 A KR 910001941A KR 1019890009316 A KR1019890009316 A KR 1019890009316A KR 890009316 A KR890009316 A KR 890009316A KR 910001941 A KR910001941 A KR 910001941A
- Authority
- KR
- South Korea
- Prior art keywords
- deposition
- forming
- gate
- oxide film
- fet manufacturing
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 230000008021 deposition Effects 0.000 claims 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
Abstract
내용 없음No content
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본발명에 따른 모오스 FET 제조 공정도.2 is a process diagram of MOS FET manufacturing according to the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019890009316A KR0142875B1 (en) | 1989-06-30 | 1989-06-30 | Fabrication method of mosfet |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019890009316A KR0142875B1 (en) | 1989-06-30 | 1989-06-30 | Fabrication method of mosfet |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910001941A true KR910001941A (en) | 1991-01-31 |
KR0142875B1 KR0142875B1 (en) | 1998-08-17 |
Family
ID=19287712
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890009316A KR0142875B1 (en) | 1989-06-30 | 1989-06-30 | Fabrication method of mosfet |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0142875B1 (en) |
-
1989
- 1989-06-30 KR KR1019890009316A patent/KR0142875B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0142875B1 (en) | 1998-08-17 |
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E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
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Payment date: 20090327 Year of fee payment: 12 |
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